[PATCH] drm/amd/powerplay: update cached feature enablement status

Evan Quan evan.quan at amd.com
Wed Aug 21 09:24:13 UTC 2019


Need to update in cache feature enablement status after pp_feature
settings. Another fix for the commit below:
drm/amd/powerplay: implment sysfs feature status function in smu

Change-Id: I90e29b0d839df26825d5993212f6097c7ad4bebf
Signed-off-by: Evan Quan <evan.quan at amd.com>
---
 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index c663d25db5ab..04867cafb322 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -96,11 +96,13 @@ size_t smu_sys_get_pp_feature_mask(struct smu_context *smu, char *buf)
 
 int smu_sys_set_pp_feature_mask(struct smu_context *smu, uint64_t new_mask)
 {
+	struct smu_feature *feature = &smu->smu_feature;
 	int ret = 0;
 	uint32_t feature_mask[2] = { 0 };
 	uint64_t feature_2_enabled = 0;
 	uint64_t feature_2_disabled = 0;
 	uint64_t feature_enables = 0;
+	uint64_t feature_id;
 
 	ret = smu_feature_get_enabled_mask(smu, feature_mask, 2);
 	if (ret)
@@ -115,11 +117,25 @@ int smu_sys_set_pp_feature_mask(struct smu_context *smu, uint64_t new_mask)
 		ret = smu_feature_update_enable_state(smu, feature_2_enabled, true);
 		if (ret)
 			return ret;
+
+		mutex_lock(&feature->mutex);
+		for (feature_id = 0; feature_id < 64; feature_id++) {
+			if (feature_2_enabled & (1ULL << feature_id))
+				test_and_set_bit(feature_id, feature->enabled);
+		}
+		mutex_unlock(&feature->mutex);
 	}
 	if (feature_2_disabled) {
 		ret = smu_feature_update_enable_state(smu, feature_2_disabled, false);
 		if (ret)
 			return ret;
+
+		mutex_lock(&feature->mutex);
+		for (feature_id = 0; feature_id < 64; feature_id++) {
+			if (feature_2_disabled & (1ULL << feature_id))
+				test_and_clear_bit(feature_id, feature->enabled);
+		}
+		mutex_unlock(&feature->mutex);
 	}
 
 	return ret;
-- 
2.23.0



More information about the amd-gfx mailing list