[PATCH 1/2] drm/amd/powerplay: correct Vega20 dpm level related settings
Deucher, Alexander
Alexander.Deucher at amd.com
Thu Aug 22 12:49:11 UTC 2019
Acked-by: Alex Deucher <alexander.deucher at amd.com>
________________________________
From: Quan, Evan <Evan.Quan at amd.com>
Sent: Thursday, August 22, 2019 6:21 AM
To: Quan, Evan <Evan.Quan at amd.com>; amd-gfx at lists.freedesktop.org <amd-gfx at lists.freedesktop.org>
Cc: Deucher, Alexander <Alexander.Deucher at amd.com>
Subject: RE: [PATCH 1/2] drm/amd/powerplay: correct Vega20 dpm level related settings
Ping..
> -----Original Message-----
> From: Evan Quan <evan.quan at amd.com>
> Sent: Wednesday, August 21, 2019 4:42 PM
> To: amd-gfx at lists.freedesktop.org
> Cc: Quan, Evan <Evan.Quan at amd.com>
> Subject: [PATCH 1/2] drm/amd/powerplay: correct Vega20 dpm level related
> settings
>
> Correct the settings for auto mode and skip the unnecessary settings for
> dcefclk and fclk.
>
> Change-Id: I7e6ca75ce86b4d5cd44920a9fbc71b6f36ea3c49
> Signed-off-by: Evan Quan <evan.quan at amd.com>
> ---
> .../drm/amd/powerplay/hwmgr/vega20_hwmgr.c | 60
> +++++++++++++++++--
> 1 file changed, 54 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
> b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
> index 0516c294b377..cc52d5c8ccf9 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
> @@ -2349,12 +2349,16 @@ static int vega20_force_dpm_highest(struct
> pp_hwmgr *hwmgr)
> data->dpm_table.soc_table.dpm_state.soft_max_level =
> data->dpm_table.soc_table.dpm_levels[soft_level].value;
>
> - ret = vega20_upload_dpm_min_level(hwmgr, 0xFFFFFFFF);
> + ret = vega20_upload_dpm_min_level(hwmgr,
> FEATURE_DPM_GFXCLK_MASK |
> + FEATURE_DPM_UCLK_MASK
> |
> +
> FEATURE_DPM_SOCCLK_MASK);
> PP_ASSERT_WITH_CODE(!ret,
> "Failed to upload boot level to highest!",
> return ret);
>
> - ret = vega20_upload_dpm_max_level(hwmgr, 0xFFFFFFFF);
> + ret = vega20_upload_dpm_max_level(hwmgr,
> FEATURE_DPM_GFXCLK_MASK |
> + FEATURE_DPM_UCLK_MASK
> |
> +
> FEATURE_DPM_SOCCLK_MASK);
> PP_ASSERT_WITH_CODE(!ret,
> "Failed to upload dpm max level to highest!",
> return ret);
> @@ -2387,12 +2391,16 @@ static int vega20_force_dpm_lowest(struct
> pp_hwmgr *hwmgr)
> data->dpm_table.soc_table.dpm_state.soft_max_level =
> data->dpm_table.soc_table.dpm_levels[soft_level].value;
>
> - ret = vega20_upload_dpm_min_level(hwmgr, 0xFFFFFFFF);
> + ret = vega20_upload_dpm_min_level(hwmgr,
> FEATURE_DPM_GFXCLK_MASK |
> + FEATURE_DPM_UCLK_MASK
> |
> +
> FEATURE_DPM_SOCCLK_MASK);
> PP_ASSERT_WITH_CODE(!ret,
> "Failed to upload boot level to highest!",
> return ret);
>
> - ret = vega20_upload_dpm_max_level(hwmgr, 0xFFFFFFFF);
> + ret = vega20_upload_dpm_max_level(hwmgr,
> FEATURE_DPM_GFXCLK_MASK |
> + FEATURE_DPM_UCLK_MASK
> |
> +
> FEATURE_DPM_SOCCLK_MASK);
> PP_ASSERT_WITH_CODE(!ret,
> "Failed to upload dpm max level to highest!",
> return ret);
> @@ -2403,14 +2411,54 @@ static int vega20_force_dpm_lowest(struct
> pp_hwmgr *hwmgr)
>
> static int vega20_unforce_dpm_levels(struct pp_hwmgr *hwmgr) {
> + struct vega20_hwmgr *data =
> + (struct vega20_hwmgr *)(hwmgr->backend);
> + uint32_t soft_min_level, soft_max_level;
> int ret = 0;
>
> - ret = vega20_upload_dpm_min_level(hwmgr, 0xFFFFFFFF);
> + /* gfxclk soft min/max settings */
> + soft_min_level =
> + vega20_find_lowest_dpm_level(&(data-
> >dpm_table.gfx_table));
> + soft_max_level =
> + vega20_find_highest_dpm_level(&(data-
> >dpm_table.gfx_table));
> +
> + data->dpm_table.gfx_table.dpm_state.soft_min_level =
> + data-
> >dpm_table.gfx_table.dpm_levels[soft_min_level].value;
> + data->dpm_table.gfx_table.dpm_state.soft_max_level =
> + data-
> >dpm_table.gfx_table.dpm_levels[soft_max_level].value;
> +
> + /* uclk soft min/max settings */
> + soft_min_level =
> + vega20_find_lowest_dpm_level(&(data-
> >dpm_table.mem_table));
> + soft_max_level =
> + vega20_find_highest_dpm_level(&(data-
> >dpm_table.mem_table));
> +
> + data->dpm_table.mem_table.dpm_state.soft_min_level =
> + data-
> >dpm_table.mem_table.dpm_levels[soft_min_level].value;
> + data->dpm_table.mem_table.dpm_state.soft_max_level =
> + data-
> >dpm_table.mem_table.dpm_levels[soft_max_level].value;
> +
> + /* socclk soft min/max settings */
> + soft_min_level =
> + vega20_find_lowest_dpm_level(&(data-
> >dpm_table.soc_table));
> + soft_max_level =
> + vega20_find_highest_dpm_level(&(data-
> >dpm_table.soc_table));
> +
> + data->dpm_table.soc_table.dpm_state.soft_min_level =
> + data-
> >dpm_table.soc_table.dpm_levels[soft_min_level].value;
> + data->dpm_table.soc_table.dpm_state.soft_max_level =
> + data-
> >dpm_table.soc_table.dpm_levels[soft_max_level].value;
> +
> + ret = vega20_upload_dpm_min_level(hwmgr,
> FEATURE_DPM_GFXCLK_MASK |
> + FEATURE_DPM_UCLK_MASK
> |
> +
> FEATURE_DPM_SOCCLK_MASK);
> PP_ASSERT_WITH_CODE(!ret,
> "Failed to upload DPM Bootup Levels!",
> return ret);
>
> - ret = vega20_upload_dpm_max_level(hwmgr, 0xFFFFFFFF);
> + ret = vega20_upload_dpm_max_level(hwmgr,
> FEATURE_DPM_GFXCLK_MASK |
> + FEATURE_DPM_UCLK_MASK
> |
> +
> FEATURE_DPM_SOCCLK_MASK);
> PP_ASSERT_WITH_CODE(!ret,
> "Failed to upload DPM Max Levels!",
> return ret);
> --
> 2.23.0
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