[PATCH 2/2] drm/amd/powerplay: pre-check the SMU state before issuing message

[Feng, Kenneth]

Got it. Thanks.
Reviewed-by: Kenneth Feng <kenneth.feng at amd.com<mailto:kenneth.feng at amd.com>

在 2019年12月4日，下午6:23，Quan, Evan <Evan.Quan at amd.com<mailto:Evan.Quan at amd.com>> 写道：

The abort operation is added in smu_v11_0_send_msg_with_param.
And for smu_v11_0_wait_for_response, yes, it's only code factoring.

-----Original Message-----
From: Feng, Kenneth <Kenneth.Feng at amd.com<mailto:Kenneth.Feng at amd.com>>
Sent: Wednesday, December 4, 2019 6:14 PM
To: Quan, Evan <Evan.Quan at amd.com<mailto:Evan.Quan at amd.com>>
Cc: amd-gfx at lists.freedesktop.org<mailto:amd-gfx at lists.freedesktop.org>
Subject: Re: [PATCH 2/2] drm/amd/powerplay: pre-check the SMU state before
issuing message

Hi Evan,
The original design is also aborting sending the message because of a ‘break’
there.
Your patch is for code factoring?
Thanks.

在 2019年12月4日，下午5:53，Evan Quan <Evan.Quan at amd.com<mailto:Evan.Quan at amd.com>> 写
道：

[CAUTION: External Email]

Abort the message issuing if the SMU was not in the right state.

Change-Id: Ida9f911e051f6e78de4f475956c78637e56e6ea3
Signed-off-by: Evan Quan <evan.quan at amd.com<mailto:evan.quan at amd.com>>
---
drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 16 ++++++++--------
drivers/gpu/drm/amd/powerplay/smu_v12_0.c | 16 ++++++++--------
2 files changed, 16 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index 325ec4864f90..d84c7f5fb01a 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -68,15 +68,13 @@ static int smu_v11_0_wait_for_response(struct
smu_context *smu)
      for (i = 0; i < timeout; i++) {
              cur_value = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90);
              if ((cur_value & MP1_C2PMSG_90__CONTENT_MASK) != 0)
-                       break;
+                       return cur_value == 0x1 ? 0 : -EIO;
+
              udelay(1);
      }

      /* timeout means wrong logic */
-       if (i == timeout)
-               return -ETIME;
-
-       return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90) == 0x1 ? 0 :
-EIO;
+       return -ETIME;
}

int
@@ -92,9 +90,11 @@ smu_v11_0_send_msg_with_param(struct
smu_context *smu,
              return index;

      ret = smu_v11_0_wait_for_response(smu);
-       if (ret)
-               pr_err("failed send message: %10s (%d) \tparam: 0x%08x
response %#x\n",
-                      smu_get_message_name(smu, msg), index, param, ret);
+       if (ret) {
+               pr_err("Msg issuing pre-check failed and "
+                      "SMU may be not in the right state!\n");
+               return ret;
+       }

      WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0);

diff --git a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
index 7f5f7e12a41e..a638326ba1b7 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c
@@ -56,15 +56,13 @@ int smu_v12_0_wait_for_response(struct
smu_context *smu)
      for (i = 0; i < adev->usec_timeout; i++) {
              cur_value = RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90);
              if ((cur_value & MP1_C2PMSG_90__CONTENT_MASK) != 0)
-                       break;
+                       return cur_value == 0x1 ? 0 : -EIO;
+
              udelay(1);
      }

      /* timeout means wrong logic */
-       if (i == adev->usec_timeout)
-               return -ETIME;
-
-       return RREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90) == 0x1 ? 0 :
-EIO;
+       return -ETIME;
}

int
@@ -80,9 +78,11 @@ smu_v12_0_send_msg_with_param(struct
smu_context *smu,
              return index;

      ret = smu_v12_0_wait_for_response(smu);
-       if (ret)
-               pr_err("Failed to send message 0x%x, response 0x%x, param
0x%x\n",
-                      index, ret, param);
+       if (ret) {
+               pr_err("Msg issuing pre-check failed and "
+                      "SMU may be not in the right state!\n");
+               return ret;
+       }

      WREG32_SOC15(MP1, 0, mmMP1_SMN_C2PMSG_90, 0);

--
2.24.0

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