[PATCH 4/5] drm/amd/powerplay: correct Navi10 VCN powergate control

[Wang, Kevin(Yang)]

It's not necessary in the current code,
but if you update the implementation of the API one day,
your code won't look so strong.
I don't recommend it.

Best Regards,
Kevin


________________________________
From: Quan, Evan <Evan.Quan at amd.com>
Sent: Monday, July 22, 2019 2:42:26 PM
To: Wang, Kevin(Yang) <Kevin1.Wang at amd.com>; Feng, Kenneth <Kenneth.Feng at amd.com>; amd-gfx at lists.freedesktop.org <amd-gfx at lists.freedesktop.org>
Cc: Deucher, Alexander <Alexander.Deucher at amd.com>
Subject: RE: [PATCH 4/5] drm/amd/powerplay: correct Navi10 VCN powergate control


That does not really matters. The API will still return success even on smu_feature_set_enabled failure. It does not care about smu_feature_set_enabled failure.

But it helps me find another issue(about the naming smu_feature_set_enabled). I just sent out a patch to address that.



Regards,

Evan

From: Wang, Kevin(Yang) <Kevin1.Wang at amd.com>
Sent: Monday, July 22, 2019 1:39 PM
To: Feng, Kenneth <Kenneth.Feng at amd.com>; Quan, Evan <Evan.Quan at amd.com>; amd-gfx at lists.freedesktop.org
Cc: Deucher, Alexander <Alexander.Deucher at amd.com>
Subject: Re: [PATCH 4/5] drm/amd/powerplay: correct Navi10 VCN powergate control



you should check return value in smu anytime.



+       smu_feature_set_enabled(smu, SMU_FEATURE_VCN_PG_BIT, enable);
+



Reviewed-by: Kevin Wang <kevin1.wang at amd.com<mailto:kevin1.wang at amd.com>>



Best Regards,
kevin

________________________________

From: amd-gfx <amd-gfx-bounces at lists.freedesktop.org<mailto:amd-gfx-bounces at lists.freedesktop.org>> on behalf of Feng, Kenneth <Kenneth.Feng at amd.com<mailto:Kenneth.Feng at amd.com>>
Sent: Monday, July 22, 2019 12:28:40 PM
To: Quan, Evan <Evan.Quan at amd.com<mailto:Evan.Quan at amd.com>>; amd-gfx at lists.freedesktop.org<mailto:amd-gfx at lists.freedesktop.org> <amd-gfx at lists.freedesktop.org<mailto:amd-gfx at lists.freedesktop.org>>
Cc: Deucher, Alexander <Alexander.Deucher at amd.com<mailto:Alexander.Deucher at amd.com>>; Quan, Evan <Evan.Quan at amd.com<mailto:Evan.Quan at amd.com>>
Subject: RE: [PATCH 4/5] drm/amd/powerplay: correct Navi10 VCN powergate control



Reviewed-by: Kenneth Feng <kenneth.feng at amd.com<mailto:kenneth.feng at amd.com>>


-----Original Message-----
From: amd-gfx [mailto:amd-gfx-bounces at lists.freedesktop.org] On Behalf Of Evan Quan
Sent: Monday, July 22, 2019 11:16 AM
To: amd-gfx at lists.freedesktop.org<mailto:amd-gfx at lists.freedesktop.org>
Cc: Deucher, Alexander <Alexander.Deucher at amd.com<mailto:Alexander.Deucher at amd.com>>; Quan, Evan <Evan.Quan at amd.com<mailto:Evan.Quan at amd.com>>
Subject: [PATCH 4/5] drm/amd/powerplay: correct Navi10 VCN powergate control

[CAUTION: External Email]

No VCN DPM bit check as that's different from VCN PG. Also no extra check for possible double enablement/disablement as that's already done by VCN.

Change-Id: I59c63829cf4dcb8093fde1ca8245b613ab2d90df
Signed-off-by: Evan Quan <evan.quan at amd.com<mailto:evan.quan at amd.com>>
---
 drivers/gpu/drm/amd/powerplay/navi10_ppt.c | 26 ++++++++--------------
 1 file changed, 9 insertions(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
index c8ce9bbae276..2198d373d38c 100644
--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
@@ -591,27 +591,19 @@ static int navi10_set_default_dpm_table(struct smu_context *smu)  static int navi10_dpm_set_uvd_enable(struct smu_context *smu, bool enable)  {
        int ret = 0;
-       struct smu_power_context *smu_power = &smu->smu_power;
-       struct smu_power_gate *power_gate = &smu_power->power_gate;

-       if (enable && power_gate->uvd_gated) {
-               if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT)) {
-                       ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 1);
-                       if (ret)
-                               return ret;
-               }
-               power_gate->uvd_gated = false;
+       if (enable) {
+               ret = smu_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 1);
+               if (ret)
+                       return ret;
        } else {
-               if (!enable && !power_gate->uvd_gated) {
-                       if (smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT)) {
-                               ret = smu_send_smc_msg(smu, SMU_MSG_PowerDownVcn);
-                               if (ret)
-                                       return ret;
-                       }
-                       power_gate->uvd_gated = true;
-               }
+               ret = smu_send_smc_msg(smu, SMU_MSG_PowerDownVcn);
+               if (ret)
+                       return ret;
        }

+       smu_feature_set_enabled(smu, SMU_FEATURE_VCN_PG_BIT, enable);
+
        return 0;
 }

--
2.22.0

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