[PATCH] drm/amdkfd: Fix byte align on VegaM

[Russell, Kent]

I'll push this, I was just wondering if Felix could confirm if the TLB workaround was only for Tonga/Topaz, in which case we could check for that instead of having to expand the list in situations like this, to say "if FAMILY_VI && (TOPAZ || TONGA) then". That way it's explicitly applying the workaround to the affected ASICs instead of implicitly not-applying the workaround to unaffected ASICs.

Kent

From: Deucher, Alexander <Alexander.Deucher at amd.com>
Sent: Tuesday, July 23, 2019 11:16 AM
To: Russell, Kent <Kent.Russell at amd.com>; amd-gfx at lists.freedesktop.org
Subject: Re: [PATCH] drm/amdkfd: Fix byte align on VegaM

Reviewed-by: Alex Deucher <alexander.deucher at amd.com<mailto:alexander.deucher at amd.com>>
________________________________
From: amd-gfx <amd-gfx-bounces at lists.freedesktop.org<mailto:amd-gfx-bounces at lists.freedesktop.org>> on behalf of Russell, Kent <Kent.Russell at amd.com<mailto:Kent.Russell at amd.com>>
Sent: Tuesday, July 23, 2019 10:22 AM
To: amd-gfx at lists.freedesktop.org<mailto:amd-gfx at lists.freedesktop.org> <amd-gfx at lists.freedesktop.org<mailto:amd-gfx at lists.freedesktop.org>>
Cc: Russell, Kent <Kent.Russell at amd.com<mailto:Kent.Russell at amd.com>>
Subject: [PATCH] drm/amdkfd: Fix byte align on VegaM

This was missed during the addition of VegaM support

Change-Id: I61c8fbbea77338126e3ebdfa74c286b665bdd670
Signed-off-by: Kent Russell <kent.russell at amd.com<mailto:kent.russell at amd.com>>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
index f5ecf28eb37c..3179117ac434 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
@@ -1139,7 +1139,8 @@ int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(
                         adev->asic_type != CHIP_FIJI &&
                         adev->asic_type != CHIP_POLARIS10 &&
                         adev->asic_type != CHIP_POLARIS11 &&
-                       adev->asic_type != CHIP_POLARIS12) ?
+                       adev->asic_type != CHIP_POLARIS12 &&
+                       adev->asic_type != CHIP_VEGAM) ?
                         VI_BO_SIZE_ALIGN : 1;

         mapping_flags = AMDGPU_VM_PAGE_READABLE;
--
2.17.1

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