[PATCH v5 0/4] Enable S/G for Picasso

Michel Dänzer michel at daenzer.net
Thu Jul 25 14:39:38 UTC 2019

On 2019-07-25 4:24 p.m., Andrey Grodzovsky wrote:
> First patches fixes a hard hang introduced by placing the display BO in 
> GTT memory because of HW issues with cached mappings. Second patch does
> some minor reafactoring to resue code in thrid patch. Third patch adds
> check for USWC support as condition to placing APUs scanout BO in GTT.
> Last patch enables S/G.
> Andrey Grodzovsky (3):
>   drm/amdgpu: Fix hard hang for S/G display BOs.
>   drm/amdgpu: Create helper to clear AMDGPU_GEM_CREATE_CPU_GTT_USWC
>   drm/amdgpu: Add check for USWC support for
>     amdgpu_display_supported_domains
> Shirish S (1):
>   drm/amd/display: enable S/G for RAVEN chip

Patches 2 & 3 are

Acked-by: Michel Dänzer <michel.daenzer at amd.com>

Earthling Michel Dänzer               |              https://www.amd.com
Libre software enthusiast             |             Mesa and X developer

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