[PATCH v5 4/4] drm/amd/display: enable S/G for RAVEN chip

[Grodzovsky, Andrey]

Totally agree, me or Shirish will add a new patch for this as I've 
already commuted the series.

Andrey

On 7/26/19 5:03 AM, Michel Dänzer wrote:
> On 2019-07-26 9:14 a.m., Christian König wrote:
>> Am 25.07.19 um 16:24 schrieb Andrey Grodzovsky:
>>> From: Shirish S <shirish.s at amd.com>
>>>
>>> enables gpu_vm_support in dm and adds
>>> AMDGPU_GEM_DOMAIN_GTT as supported domain
>>>
>>> v2:
>>> Move BO placement logic into amdgpu_display_supported_domains
>>>
>>> v3:
>>> Use amdgpu_bo_validate_uswc in amdgpu_display_supported_domains.
>>>
>>> v4:
>>> amdgpu_bo_validate_uswc moved to sepperate patch.
>>>
>>> Change-Id: If34300beaa60be2d36170b7b5b096ec644502b20
>>> Signed-off-by: Shirish S <shirish.s at amd.com>
>>> Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky at amd.com>
>>> ---
>>>    drivers/gpu/drm/amd/amdgpu/amdgpu_display.c       | 2 +-
>>>    drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +-
>>>    2 files changed, 2 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
>>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
>>> index cac9975..73045a3 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
>>> @@ -505,7 +505,7 @@ uint32_t amdgpu_display_supported_domains(struct
>>> amdgpu_device *adev)
>>>         * APUs. So force the BO placement to VRAM in case this
>>> architecture
>>>         * will not allow USWC mappings.
>>>         */
>>> -    if (adev->asic_type >= CHIP_CARRIZO && adev->asic_type <
>>> CHIP_RAVEN &&
>>> +    if (adev->asic_type >= CHIP_CARRIZO && adev->asic_type <=
>>> CHIP_RAVEN &&
>> This whole approach is incorrect since we don't check the flags of the
>> actually BO used for scanout any more.
>>
>> As I wrote before it is still perfectly possible and valid that
>> userspace never sets this flag.
> Oh right, now I get what you meant before!
>
> I guess amdgpu_display_supported_domains needs to take the BO flags as a
> parameter, and also check that AMDGPU_GEM_CREATE_CPU_GTT_USWC is
> actually set.
>
>