[PATCH 2/2] drm/amdgpu/display: switch udelay to msleep

[Kazlauskas, Nicholas]

On 6/25/19 9:58 AM, Alex Deucher wrote:
> We may need to sleep for up to 80ms:
> 
> /* First DPCD read after VDD ON can fail if the particular board
>   * does not have HPD pin wired correctly. So if DPCD read fails,
>   * which it should never happen, retry a few times. Target worst
>   * case scenario of 80 ms.
>   */
> 
> Switch udelay to msleep to avoid limits on arm.
> 
> Signed-off-by: Alex Deucher <alexander.deucher at amd.com>

Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas at amd.com>

Technically this still mismatches what the comment says above the block, 
but this retains the same behavior as before.

Nicholas Kazlauskas

> ---
>   drivers/gpu/drm/amd/display/dc/core/dc_link.c | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
> index d6f8be654c2e..c17db5c144aa 100644
> --- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
> +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
> @@ -550,7 +550,7 @@ static void read_edp_current_link_settings_on_detect(struct dc_link *link)
>   			break;
>   		}
>   
> -		udelay(8000);
> +		msleep(8);
>   	}
>   
>   	ASSERT(status == DC_OK);
>