[PATCH 1/3] drm/amdgpu: change Vega IH ring 1 config

[Zeng, Oak]

Copied register definitions below. I guess with this change, you changed how the IH block treat new interrupt when ring is full. Before this change, IH keep new interrupt in the ring and overwrite oldest interrupt. After your change, IH will simply drop new interrupt and keep old interrupt in the ring (keep wptr unchanged).



Is above understanding correct? If yes, can you explain why the new scheme is more reliable? If this is more reliable, should we use this scheme for all 3 interrupt ring?


RB_FULL_DRAIN_ENABLE

9

0x0

When Ring Buffer is full, this enables draining of interrupts to prevent back pressure to IH clients.
 POSSIBLE VALUES:
      00 - Disable

WPTR_OVERFLOW_ENABLE

16

0x1

Ring Buffer write pointer overflow.
 POSSIBLE VALUES:
      00 - Disable
      01 - Enable






Regards,

Oak



-----Original Message-----
From: amd-gfx <amd-gfx-bounces at lists.freedesktop.org> On Behalf Of Christian König
Sent: Wednesday, March 6, 2019 4:29 AM
To: amd-gfx at lists.freedesktop.org
Subject: Re: [PATCH 1/3] drm/amdgpu: change Vega IH ring 1 config



Ping? Can anybody review this?



Thanks,

Christian.



Am 04.03.19 um 20:10 schrieb Christian König:

> Disable overflow and enable full drain. This makes fault handling on

> ring 1 much more reliable since we don't generate back pressure any more.

>

> Signed-off-by: Christian König <christian.koenig at amd.com<mailto:christian.koenig at amd.com>>

> ---

>   drivers/gpu/drm/amd/amdgpu/vega10_ih.c | 4 ++++

>   1 file changed, 4 insertions(+)

>

> diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c

> b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c

> index 6d1f804277f8..d4a3cc413af8 100644

> --- a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c

> +++ b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c

> @@ -203,6 +203,10 @@ static int vega10_ih_irq_init(struct

> amdgpu_device *adev)

>

>                            ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1);

>                            ih_rb_cntl = vega10_ih_rb_cntl(ih, ih_rb_cntl);

> +                         ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,

> +                                                                         WPTR_OVERFLOW_ENABLE, 0);

> +                         ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,

> +                                                                         RB_FULL_DRAIN_ENABLE, 1);

>                            WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL_RING1, ih_rb_cntl);

>

>                            /* set rptr, wptr to 0 */



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