[PATCH] drm/amd/amdgpu/sriov ip block setting of Arcturus

[Deucher, Alexander]

________________________________
From: amd-gfx <amd-gfx-bounces at lists.freedesktop.org> on behalf of Jack Zhang <Jack.Zhang1 at amd.com>
Sent: Monday, September 30, 2019 1:00 AM
To: amd-gfx at lists.freedesktop.org <amd-gfx at lists.freedesktop.org>
Cc: Zhang, Jack (Jian) <Jack.Zhang1 at amd.com>
Subject: [PATCH] drm/amd/amdgpu/sriov ip block setting of Arcturus

Add ip block setting for Arcturus SRIOV

1.PSP need to be initialized before IH.
2.SMU doesn't need to be initialized at kmd driver.
3.Arcturus doesn't support DCE hardware,it needs to skip
  register access to DCE.

Signed-off-by: Jack Zhang <Jack.Zhang1 at amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 10 ++++++----
 drivers/gpu/drm/amd/amdgpu/soc15.c    | 19 +++++++++++++++----
 2 files changed, 21 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index 95a9a5f5..44023bd 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -1330,11 +1330,13 @@ static int gmc_v9_0_hw_init(void *handle)
         gmc_v9_0_init_golden_registers(adev);

         if (adev->mode_info.num_crtc) {
-               /* Lockout access through VGA aperture*/
-               WREG32_FIELD15(DCE, 0, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
+               if (adev->asic_type != CHIP_ARCTURUS) {
+                       /* Lockout access through VGA aperture*/
+                       WREG32_FIELD15(DCE, 0, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);

-               /* disable VGA render */
-               WREG32_FIELD15(DCE, 0, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
+                       /* disable VGA render */
+                       WREG32_FIELD15(DCE, 0, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
+               }
         }

This is a general bug fix and should be split out into a separate patch.

Alex

         r = gmc_v9_0_gart_enable(adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
index dbd790e..ac181e3 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -754,14 +754,25 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev)
         case CHIP_ARCTURUS:
                 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
                 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
-               amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
-               if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
-                       amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
+
+               /* For MI100 SR-IOV, PSP need to be initialized before IH */
+               if (amdgpu_sriov_vf(adev)) {
+                       if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
+                               amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
+                       amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
+               } else {
+                       amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
+                       if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP))
+                               amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);
+               }
+
                 if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
                         amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
                 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
                 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
-               amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
+               if (!amdgpu_sriov_vf(adev))
+                       amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
+
                 if (unlikely(adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT))
                         amdgpu_device_ip_block_add(adev, &vcn_v2_5_ip_block);
                 break;
--
2.7.4

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