[PATCH 7/8] drm/amd/powerplay: implement the interface for setting sclk/uclk profile_peak level

[Wang, Kevin(Yang)]

this patch is not needed for apu.
by default, the smu will use max value as peak value.

refs:smu_default_set_performance_level

Best Regards,
Kevin

________________________________
From: amd-gfx <amd-gfx-bounces at lists.freedesktop.org> on behalf of Liang, Prike <Prike.Liang at amd.com>
Sent: Thursday, September 26, 2019 11:50 AM
To: amd-gfx at lists.freedesktop.org <amd-gfx at lists.freedesktop.org>
Cc: Liang, Prike <Prike.Liang at amd.com>; Quan, Evan <Evan.Quan at amd.com>; Huang, Ray <Ray.Huang at amd.com>; keneth.feng at amd.com <keneth.feng at amd.com>
Subject: [PATCH 7/8] drm/amd/powerplay: implement the interface for setting sclk/uclk profile_peak level

Add the interface for setting sclk and uclk peak frequency.

Signed-off-by: Prike Liang <Prike.Liang at amd.com>
---
 drivers/gpu/drm/amd/powerplay/renoir_ppt.c | 40 ++++++++++++++++++++++++++++++
 1 file changed, 40 insertions(+)

diff --git a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
index 151d78e..c63518a 100644
--- a/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/renoir_ppt.c
@@ -510,6 +510,45 @@ static int renoir_set_power_profile_mode(struct smu_context *smu, long *input, u
         return 0;
 }

+static int renoir_set_peak_clock_by_device(struct smu_context *smu)
+{
+       int ret = 0;
+       uint32_t sclk_freq = 0, uclk_freq = 0;
+
+       ret = smu_get_dpm_freq_range(smu, SMU_SCLK, NULL, &sclk_freq);
+       if (ret)
+               return ret;
+
+       ret = smu_set_soft_freq_range(smu, SMU_SCLK, sclk_freq, sclk_freq);
+       if (ret)
+               return ret;
+
+       ret = smu_get_dpm_freq_range(smu, SMU_UCLK, NULL, &uclk_freq);
+       if (ret)
+               return ret;
+
+       ret = smu_set_soft_freq_range(smu, SMU_UCLK, uclk_freq, uclk_freq);
+       if (ret)
+               return ret;
+
+       return ret;
+}
+
+static int renoir_set_performance_level(struct smu_context *smu, enum amd_dpm_forced_level level)
+{
+       int ret = 0;
+
+       switch (level) {
+       case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
+               ret = renoir_set_peak_clock_by_device(smu);
+               break;
+       default:
+               ret = -EINVAL;
+               break;
+       }
+
+       return ret;
+}

 static const struct pptable_funcs renoir_ppt_funcs = {
         .get_smu_msg_index = renoir_get_smu_msg_index,
@@ -526,6 +565,7 @@ static const struct pptable_funcs renoir_ppt_funcs = {
         .get_profiling_clk_mask = renoir_get_profiling_clk_mask,
         .force_clk_levels = renoir_force_clk_levels,
         .set_power_profile_mode = renoir_set_power_profile_mode,
+       .set_performance_level = renoir_set_performance_level,
 };

 void renoir_set_ppt_funcs(struct smu_context *smu)
--
2.7.4

_______________________________________________
amd-gfx mailing list
amd-gfx at lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <https://lists.freedesktop.org/archives/amd-gfx/attachments/20190926/8025a0e6/attachment-0001.html>