[PATCH] drm/amd/powerplay: correct UVD/VCE PG state on custom pptable uploading

[Deucher, Alexander]

[AMD Official Use Only - Internal Distribution Only]

Acked-by: Alex Deucher <alexander.deucher at amd.com>
________________________________
From: Quan, Evan <Evan.Quan at amd.com>
Sent: Friday, August 7, 2020 5:31 AM
To: amd-gfx at lists.freedesktop.org <amd-gfx at lists.freedesktop.org>
Cc: Deucher, Alexander <Alexander.Deucher at amd.com>; Quan, Evan <Evan.Quan at amd.com>
Subject: [PATCH] drm/amd/powerplay: correct UVD/VCE PG state on custom pptable uploading

The UVD/VCE PG state is managed by UVD and VCE IP. It's error-prone to
assume the bootup state in SMU based on the dpm status.

Change-Id: Ib88298ab9812d7d242592bcd55eea140bef6696a
Signed-off-by: Evan Quan <evan.quan at amd.com>
---
 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c | 6 ------
 1 file changed, 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
index acc926c20c55..da84012b7fd5 100644
--- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
+++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c
@@ -1645,12 +1645,6 @@ static void vega20_init_powergate_state(struct pp_hwmgr *hwmgr)

         data->uvd_power_gated = true;
         data->vce_power_gated = true;
-
-       if (data->smu_features[GNLD_DPM_UVD].enabled)
-               data->uvd_power_gated = false;
-
-       if (data->smu_features[GNLD_DPM_VCE].enabled)
-               data->vce_power_gated = false;
 }

 static int vega20_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
--
2.28.0

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