[PATCH] drm/amd/display: disable dcn10 pipe split by default

[Wu, Hersen]

[AMD Official Use Only - Internal Distribution Only]

[Why] the initial purpose of dcn10 pipe split is to support
some high bandwidth mode which requires dispclk greater
than max dispclk. By initial bring up power measurement
data, it showed power consumption is less with pipe split
for dcn block. This could be reason for enable pipe split
by default. By battery life measurement of some Chromebooks,
result shows battery life is longer with pipe split disabled.

[How] disable pipe split by default. Pipe split could be
still enabled when required dispclk is greater than max dispclk.

Signed-off-by: hersen wu <hersenxs.wu at amd.com>
---
 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
index bdc37831535e..17eafe209946 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c
@@ -608,8 +608,8 @@ static const struct dc_debug_options debug_defaults_drv = {
  .disable_pplib_clock_request = false,
  .disable_pplib_wm_range = false,
  .pplib_wm_report_mode = WM_REPORT_DEFAULT,
- .pipe_split_policy = MPC_SPLIT_DYNAMIC,
- .force_single_disp_pipe_split = true,
+ .pipe_split_policy = MPC_SPLIT_AVOID,
+ .force_single_disp_pipe_split = false,
  .disable_dcc = DCC_ENABLE,
  .voltage_align_fclk = true,
  .disable_stereo_support = true,
--
2.17.1


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