[PATCH] drm/amdgpu: resolved bug in UMC 6 error counter query

[Clements, John]

[AMD Public Use]

Hello Tao,

That is an interesting suggestion, I agree that there is a little bit of duplicate code with  the same for loops being used in multiple functions.

My only concern with implementing the loops in a macro is code readability.

I’ll have to think about the trade off between the duplicate code and code readability more.

Thank you,
John Clements

From: Zhou1, Tao <Tao.Zhou1 at amd.com>
Sent: Friday, January 3, 2020 10:53 AM
To: Clements, John <John.Clements at amd.com>; amd-gfx at lists.freedesktop.org; Zhang, Hawking <Hawking.Zhang at amd.com>
Subject: RE: [PATCH] drm/amdgpu: resolved bug in UMC 6 error counter query


[AMD Public Use]

I think we can implement it by only updating amdgpu_umc_for_each_channel macro, here is an example:

#define amdgpu_umc_for_each_channel(func)        \
        struct ras_err_data *err_data = \
                        (struct ras_err_data *)ras_error_status;        \
        uint32_t umc_inst, channel_inst, umc_reg_offset, channel_index; \
        for (umc_inst = 0; umc_inst < adev->umc.umc_inst_num;  \
                        umc_inst++) {   \
                umc_reg_offset = adev->umc.inst_offs * umc_inst;       \
                for (channel_inst = 0;  \
                        channel_inst < adev->umc.channel_inst_num;     \
                        channel_inst++) {       \
                        /* get channel index of interleaved memory */   \
                        channel_index = adev->umc.channel_idx_tbl[\
                                umc_inst * adev->umc.channel_inst_num + channel_inst]; \
                        (func)(adev, err_data, umc_reg_offset, channel_index); \
                        /* increase register offset for next channel */ \
                        umc_reg_offset += adev->umc.channel_offs;      \
                }       \
        }

Regards,
Tao
From: Clements, John <John.Clements at amd.com<mailto:John.Clements at amd.com>>
Sent: 2020年1月2日 18:31
To: amd-gfx at lists.freedesktop.org<mailto:amd-gfx at lists.freedesktop.org>; Zhang, Hawking <Hawking.Zhang at amd.com<mailto:Hawking.Zhang at amd.com>>; Zhou1, Tao <Tao.Zhou1 at amd.com<mailto:Tao.Zhou1 at amd.com>>
Subject: [PATCH] drm/amdgpu: resolved bug in UMC 6 error counter query


[AMD Official Use Only - Internal Distribution Only]

Added patch to resolve following issue where error counter detection was not iterating over all UMC instances/channels.
Removed support for accessing UMC error counters via MMIO.

Thank you,
John Clements
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