[PATCH 12/12] drm/amdgpu: use register distance member instead of hardcode in mmhub v9.4

[Huang Rui]

This patch updates to use register distance member instead of hardcode
in mmhub v9.4.

Signed-off-by: Huang Rui <ray.huang at amd.com>
Tested-by: AnZhong Huang <anzhong.huang at amd.com>
---
 drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c | 37 ++++++++++++++-----------
 1 file changed, 21 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c
index df2c316accde..9979f54fef57 100644
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c
@@ -57,20 +57,16 @@ u64 mmhub_v9_4_get_fb_location(struct amdgpu_device *adev)
 static void mmhub_v9_4_setup_hubid_vm_pt_regs(struct amdgpu_device *adev, int hubid,
 				uint32_t vmid, uint64_t value)
 {
-	/* two registers distance between mmVML2VC0_VM_CONTEXT0_* to
-	 * mmVML2VC0_VM_CONTEXT1_*
-	 */
-	int dist = mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32
-			- mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32;
+	struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
 
 	WREG32_SOC15_OFFSET(MMHUB, 0,
 			    mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
-			    dist * vmid + hubid * MMHUB_INSTANCE_REGISTER_OFFSET,
+			    hub->ctx_addr_distance * vmid + hubid * MMHUB_INSTANCE_REGISTER_OFFSET,
 			    lower_32_bits(value));
 
 	WREG32_SOC15_OFFSET(MMHUB, 0,
 			    mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
-			    dist * vmid + hubid * MMHUB_INSTANCE_REGISTER_OFFSET,
+			    hub->ctx_addr_distance * vmid + hubid * MMHUB_INSTANCE_REGISTER_OFFSET,
 			    upper_32_bits(value));
 
 }
@@ -301,6 +297,7 @@ static void mmhub_v9_4_disable_identity_aperture(struct amdgpu_device *adev,
 
 static void mmhub_v9_4_setup_vmid_config(struct amdgpu_device *adev, int hubid)
 {
+	struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
 	uint32_t tmp;
 	int i;
 
@@ -335,21 +332,25 @@ static void mmhub_v9_4_setup_vmid_config(struct amdgpu_device *adev, int hubid)
 				    RETRY_PERMISSION_OR_INVALID_PAGE_FAULT,
 				    !amdgpu_noretry);
 		WREG32_SOC15_OFFSET(MMHUB, 0, mmVML2VC0_VM_CONTEXT1_CNTL,
-				    hubid * MMHUB_INSTANCE_REGISTER_OFFSET + i,
-				    tmp);
+				    hubid * MMHUB_INSTANCE_REGISTER_OFFSET +
+				    i * hub->ctx_distance, tmp);
 		WREG32_SOC15_OFFSET(MMHUB, 0,
 			    mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32,
-			    hubid * MMHUB_INSTANCE_REGISTER_OFFSET + i*2, 0);
+			    hubid * MMHUB_INSTANCE_REGISTER_OFFSET +
+			    i * hub->ctx_addr_distance, 0);
 		WREG32_SOC15_OFFSET(MMHUB, 0,
 			    mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32,
-			    hubid * MMHUB_INSTANCE_REGISTER_OFFSET + i*2, 0);
+			    hubid * MMHUB_INSTANCE_REGISTER_OFFSET +
+			    i * hub->ctx_addr_distance, 0);
 		WREG32_SOC15_OFFSET(MMHUB, 0,
 				mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32,
-				hubid * MMHUB_INSTANCE_REGISTER_OFFSET + i*2,
+				hubid * MMHUB_INSTANCE_REGISTER_OFFSET +
+				i * hub->ctx_addr_distance,
 				lower_32_bits(adev->vm_manager.max_pfn - 1));
 		WREG32_SOC15_OFFSET(MMHUB, 0,
 				mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32,
-				hubid * MMHUB_INSTANCE_REGISTER_OFFSET + i*2,
+				hubid * MMHUB_INSTANCE_REGISTER_OFFSET +
+				i * hub->ctx_addr_distance,
 				upper_32_bits(adev->vm_manager.max_pfn - 1));
 	}
 }
@@ -357,16 +358,19 @@ static void mmhub_v9_4_setup_vmid_config(struct amdgpu_device *adev, int hubid)
 static void mmhub_v9_4_program_invalidation(struct amdgpu_device *adev,
 					    int hubid)
 {
+	struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
 	unsigned i;
 
 	for (i = 0; i < 18; ++i) {
 		WREG32_SOC15_OFFSET(MMHUB, 0,
 				mmVML2VC0_VM_INVALIDATE_ENG0_ADDR_RANGE_LO32,
-				hubid * MMHUB_INSTANCE_REGISTER_OFFSET + 2 * i,
+				hubid * MMHUB_INSTANCE_REGISTER_OFFSET +
+				i * hub->eng_addr_distance,
 				0xffffffff);
 		WREG32_SOC15_OFFSET(MMHUB, 0,
 				mmVML2VC0_VM_INVALIDATE_ENG0_ADDR_RANGE_HI32,
-				hubid * MMHUB_INSTANCE_REGISTER_OFFSET + 2 * i,
+				hubid * MMHUB_INSTANCE_REGISTER_OFFSET +
+				i * hub->eng_addr_distance,
 				0x1f);
 	}
 }
@@ -395,6 +399,7 @@ int mmhub_v9_4_gart_enable(struct amdgpu_device *adev)
 
 void mmhub_v9_4_gart_disable(struct amdgpu_device *adev)
 {
+	struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
 	u32 tmp;
 	u32 i, j;
 
@@ -404,7 +409,7 @@ void mmhub_v9_4_gart_disable(struct amdgpu_device *adev)
 			WREG32_SOC15_OFFSET(MMHUB, 0,
 					    mmVML2VC0_VM_CONTEXT0_CNTL,
 					    j * MMHUB_INSTANCE_REGISTER_OFFSET +
-					    i, 0);
+					    i * hub->ctx_distance, 0);
 
 		/* Setup TLB control */
 		tmp = RREG32_SOC15_OFFSET(MMHUB, 0,
-- 
2.25.1