[PATCH] drm/amd/powerplay: fix typos for clk map

Zhou1, Tao Tao.Zhou1 at amd.com
Tue Jul 21 05:33:16 UTC 2020


[AMD Official Use Only - Internal Distribution Only]

Acked-by: Tao Zhou <tao.zhou1 at amd.com>


-----Original Message-----
From: Jiansong Chen <Jiansong.Chen at amd.com>
Sent: Tuesday, July 21, 2020 12:36 PM
To: amd-gfx at lists.freedesktop.org
Cc: Zhou1, Tao <Tao.Zhou1 at amd.com>; Feng, Kenneth <Kenneth.Feng at amd.com>; Gao, Likun <Likun.Gao at amd.com>; Chen, Jiansong (Simon) <Jiansong.Chen at amd.com>
Subject: [PATCH] drm/amd/powerplay: fix typos for clk map

It should be DCLK1->PPCLK_DCLK_1 and VCLK->PPCLK_VCLK_0.

Signed-off-by: Jiansong Chen <Jiansong.Chen at amd.com>
Change-Id: Ib2239b35840d3774a0e1aa3114d2f965e6d88e7c
---
 drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
index cae8e776fafe..87eedd7c28ec 100644
--- a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
@@ -128,8 +128,8 @@ static struct cmn2asic_mapping sienna_cichlid_clk_map[SMU_CLK_COUNT] = {
 CLK_MAP(UCLK,PPCLK_UCLK),
 CLK_MAP(MCLK,PPCLK_UCLK),
 CLK_MAP(DCLK,PPCLK_DCLK_0),
-CLK_MAP(DCLK1,PPCLK_DCLK_0),
-CLK_MAP(VCLK,PPCLK_VCLK_1),
+CLK_MAP(DCLK1,PPCLK_DCLK_1),
+CLK_MAP(VCLK,PPCLK_VCLK_0),
 CLK_MAP(VCLK1,PPCLK_VCLK_1),
 CLK_MAP(DCEFCLK,PPCLK_DCEFCLK),
 CLK_MAP(DISPCLK,PPCLK_DISPCLK),
--
2.17.1



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