[PATCH 1/4] drm/amdgpu: label internally used symbols as static

Deucher, Alexander Alexander.Deucher at amd.com
Thu Jun 18 13:59:40 UTC 2020


[AMD Public Use]

Series is:
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
________________________________
From: amd-gfx <amd-gfx-bounces at lists.freedesktop.org> on behalf of Nirmoy Das <nirmoy.aiemd at gmail.com>
Sent: Thursday, June 18, 2020 9:17 AM
To: amd-gfx at lists.freedesktop.org <amd-gfx at lists.freedesktop.org>
Cc: Das, Nirmoy <Nirmoy.Das at amd.com>
Subject: [PATCH 1/4] drm/amdgpu: label internally used symbols as static

Used sparse(make C=1) to find these loose ends.

Signed-off-by: Nirmoy Das <nirmoy.das at amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c  | 2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c | 4 ++--
 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c        | 2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c        | 6 +++---
 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c        | 4 ++--
 drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c       | 4 ++--
 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c          | 4 ++--
 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c          | 2 +-
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c          | 2 +-
 9 files changed, 15 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
index b5d6274952a5..4ef38c2411ae 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
@@ -32,7 +32,7 @@
 #define mmMM_DATA               0x1
 #define HW_ID_MAX               300

-const char *hw_id_names[HW_ID_MAX] = {
+static const char *hw_id_names[HW_ID_MAX] = {
         [MP1_HWID]              = "MP1",
         [MP2_HWID]              = "MP2",
         [THM_HWID]              = "THM",
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c
index 6ae80b33182c..e811fecc540f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.c
@@ -32,7 +32,7 @@
 #define I2C_PRODUCT_INFO_ADDR_SIZE      0x2
 #define I2C_PRODUCT_INFO_OFFSET         0xC0

-bool is_fru_eeprom_supported(struct amdgpu_device *adev)
+static bool is_fru_eeprom_supported(struct amdgpu_device *adev)
 {
         /* TODO: Gaming SKUs don't have the FRU EEPROM.
          * Use this hack to address hangs on modprobe on gaming SKUs
@@ -48,7 +48,7 @@ bool is_fru_eeprom_supported(struct amdgpu_device *adev)
         return false;
 }

-int amdgpu_fru_read_eeprom(struct amdgpu_device *adev, uint32_t addrptr,
+static int amdgpu_fru_read_eeprom(struct amdgpu_device *adev, uint32_t addrptr,
                            unsigned char *buff)
 {
         int ret, size;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index 60558497f054..0723dee2958b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -583,7 +583,7 @@ static void psp_prep_ta_invoke_cmd_buf(struct psp_gfx_cmd_resp *cmd,
         cmd->cmd.cmd_invoke_cmd.ta_cmd_id        = ta_cmd_id;
 }

-int psp_ta_invoke(struct psp_context *psp,
+static int psp_ta_invoke(struct psp_context *psp,
                   uint32_t ta_cmd_id,
                   uint32_t session_id)
 {
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
index 9bfe59b70030..ab8e7c91c645 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
@@ -86,7 +86,7 @@ void amdgpu_ras_set_error_query_ready(struct amdgpu_device *adev, bool ready)
                 amdgpu_ras_get_context(adev)->error_query_ready = ready;
 }

-bool amdgpu_ras_get_error_query_ready(struct amdgpu_device *adev)
+static bool amdgpu_ras_get_error_query_ready(struct amdgpu_device *adev)
 {
         if (adev && amdgpu_ras_get_context(adev))
                 return amdgpu_ras_get_context(adev)->error_query_ready;
@@ -505,7 +505,7 @@ struct ras_manager *amdgpu_ras_find_obj(struct amdgpu_device *adev,
 }
 /* obj end */

-void amdgpu_ras_parse_status_code(struct amdgpu_device* adev,
+static void amdgpu_ras_parse_status_code(struct amdgpu_device *adev,
                                   const char*             invoke_type,
                                   const char*             block_name,
                                   enum ta_ras_status      ret)
@@ -815,7 +815,7 @@ int amdgpu_ras_error_query(struct amdgpu_device *adev,
 }

 /* Trigger XGMI/WAFL error */
-int amdgpu_ras_error_inject_xgmi(struct amdgpu_device *adev,
+static int amdgpu_ras_error_inject_xgmi(struct amdgpu_device *adev,
                                  struct ta_ras_trigger_error_input *block_info)
 {
         int ret;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index 5b42c50366c9..64b572307104 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -1113,7 +1113,7 @@ static void amdgpu_ttm_tt_unpin_userptr(struct ttm_tt *ttm)
 #endif
 }

-int amdgpu_ttm_gart_bind(struct amdgpu_device *adev,
+static int amdgpu_ttm_gart_bind(struct amdgpu_device *adev,
                                 struct ttm_buffer_object *tbo,
                                 uint64_t flags)
 {
@@ -1835,7 +1835,7 @@ static void amdgpu_ttm_training_data_block_init(struct amdgpu_device *adev)
                 (adev->gmc.mc_vram_size - GDDR6_MEM_TRAINING_OFFSET);
         ctx->train_data_size =
                 GDDR6_MEM_TRAINING_DATA_SIZE_IN_BYTES;
-
+
         DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n",
                         ctx->train_data_size,
                         ctx->p2c_train_data_offset,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
index 0891f27ba166..da233a9e429d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c
@@ -515,12 +515,12 @@ void amdgpu_detect_virtualization(struct amdgpu_device *adev)
         }
 }

-bool amdgpu_virt_access_debugfs_is_mmio(struct amdgpu_device *adev)
+static bool amdgpu_virt_access_debugfs_is_mmio(struct amdgpu_device *adev)
 {
         return amdgpu_sriov_is_debug(adev) ? true : false;
 }

-bool amdgpu_virt_access_debugfs_is_kiq(struct amdgpu_device *adev)
+static bool amdgpu_virt_access_debugfs_is_kiq(struct amdgpu_device *adev)
 {
         return amdgpu_sriov_is_normal(adev) ? true : false;
 }
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
index 0cc011f9190d..4aec76049a60 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
@@ -3039,7 +3039,7 @@ static void gfx_v7_0_mqd_init(struct amdgpu_device *adev,
         mqd->cp_hqd_active = 1;
 }

-int gfx_v7_0_mqd_commit(struct amdgpu_device *adev, struct cik_mqd *mqd)
+static int gfx_v7_0_mqd_commit(struct amdgpu_device *adev, struct cik_mqd *mqd)
 {
         uint32_t tmp;
         uint32_t mqd_reg;
@@ -5209,7 +5209,7 @@ static void gfx_v7_0_get_cu_info(struct amdgpu_device *adev)
         cu_info->lds_size = 64;
 }

-const struct amdgpu_ip_block_version gfx_v7_0_ip_block =
+static const struct amdgpu_ip_block_version gfx_v7_0_ip_block =
 {
         .type = AMD_IP_BLOCK_TYPE_GFX,
         .major = 7,
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 1d4128227ffd..efb759b62d21 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -4589,7 +4589,7 @@ static int gfx_v8_0_mqd_init(struct amdgpu_ring *ring)
         return 0;
 }

-int gfx_v8_0_mqd_commit(struct amdgpu_device *adev,
+static int gfx_v8_0_mqd_commit(struct amdgpu_device *adev,
                         struct vi_mqd *mqd)
 {
         uint32_t mqd_reg;
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index c3e59b765268..99ffc3e1fddc 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -722,7 +722,7 @@ static const u32 GFX_RLC_SRM_INDEX_CNTL_DATA_OFFSETS[] =
         mmRLC_SRM_INDEX_CNTL_DATA_7 - mmRLC_SRM_INDEX_CNTL_DATA_0,
 };

-void gfx_v9_0_rlcg_wreg(struct amdgpu_device *adev, u32 offset, u32 v)
+static void gfx_v9_0_rlcg_wreg(struct amdgpu_device *adev, u32 offset, u32 v)
 {
         static void *scratch_reg0;
         static void *scratch_reg1;
--
2.27.0

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