[PATCH] drm/amdgpu: Enable RLCG read/write interface for Sienna Cichlid

[Deucher, Alexander]

[Public]

Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
________________________________
From: amd-gfx <amd-gfx-bounces at lists.freedesktop.org> on behalf of Rohit Khaire <rohit.khaire at amd.com>
Sent: Friday, June 4, 2021 11:24 AM
To: amd-gfx at lists.freedesktop.org <amd-gfx at lists.freedesktop.org>; Deucher, Alexander <Alexander.Deucher at amd.com>; Zhang, Hawking <Hawking.Zhang at amd.com>; Deng, Emily <Emily.Deng at amd.com>; Liu, Monk <Monk.Liu at amd.com>; Zhou, Peng Ju <PengJu.Zhou at amd.com>; Chen, Horace <Horace.Chen at amd.com>
Cc: Ming, Davis <Davis.Ming at amd.com>; Khaire, Rohit <Rohit.Khaire at amd.com>; Koenig, Christian <Christian.Koenig at amd.com>
Subject: [PATCH] drm/amdgpu: Enable RLCG read/write interface for Sienna Cichlid

Enable this only for Sienna Cichild
since only Navi12 and Sienna Cichlid support SRIOV

Signed-off-by: Rohit Khaire <rohit.khaire at amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 4a50c4e9aea0..29017b18470d 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -9217,7 +9217,6 @@ static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev)
         switch (adev->asic_type) {
         case CHIP_NAVI10:
         case CHIP_NAVI14:
-       case CHIP_SIENNA_CICHLID:
         case CHIP_NAVY_FLOUNDER:
         case CHIP_VANGOGH:
         case CHIP_DIMGREY_CAVEFISH:
@@ -9225,6 +9224,7 @@ static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev)
                 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs;
                 break;
         case CHIP_NAVI12:
+       case CHIP_SIENNA_CICHLID:
                 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs_sriov;
                 break;
         default:
--
2.17.1

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