[PATCH 1/1] drm/amdgpu: Read clock counter via MMIO to reduce delay

[Wang, YuBiao]

[AMD Official Use Only]

Hello Christian,

Thank you for your comment.
Others have suggested that it isn't necessary to keep checking such a low probability issue and we may let it fail if we continuously hit this condition. So I've sent a v3 patch which change the while loop into a one-time if condition. Could you review that version? I believe you could find it in another review request email.

Thank you.
Yubiao Wang

-----Original Message-----
From: Koenig, Christian <Christian.Koenig at amd.com> 
Sent: Tuesday, June 29, 2021 7:16 PM
To: Wang, YuBiao <YuBiao.Wang at amd.com>; amd-gfx at lists.freedesktop.org
Cc: Grodzovsky, Andrey <Andrey.Grodzovsky at amd.com>; Quan, Evan <Evan.Quan at amd.com>; Chen, Horace <Horace.Chen at amd.com>; Tuikov, Luben <Luben.Tuikov at amd.com>; Deucher, Alexander <Alexander.Deucher at amd.com>; Xiao, Jack <Jack.Xiao at amd.com>; Zhang, Hawking <Hawking.Zhang at amd.com>; Liu, Monk <Monk.Liu at amd.com>; Xu, Feifei <Feifei.Xu at amd.com>; Wang, Kevin(Yang) <Kevin1.Wang at amd.com>
Subject: Re: [PATCH 1/1] drm/amdgpu: Read clock counter via MMIO to reduce delay

Am 29.06.21 um 11:47 schrieb YuBiao Wang:
> [Why]
> GPU timing counters are read via KIQ under sriov, which will introduce 
> a delay.
>
> [How]
> It could be directly read by MMIO.
>
> v2: Add additional check to prevent carryover issue.
>
> Signed-off-by: YuBiao Wang <YuBiao.Wang at amd.com>
> ---
>   drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 13 +++++++++++--
>   1 file changed, 11 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 
> b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> index ff7e9f49040e..191b9e3ee3ea 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> @@ -7610,6 +7610,7 @@ static int gfx_v10_0_soft_reset(void *handle)
>   static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev)
>   {
>   	uint64_t clock;
> +	uint64_t clock_lo, clock_hi, hi_check;
>   
>   	amdgpu_gfx_off_ctrl(adev, false);
>   	mutex_lock(&adev->gfx.gpu_clock_mutex);
> @@ -7620,8 +7621,16 @@ static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev)
>   			((uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Vangogh) << 32ULL);
>   		break;
>   	default:
> -		clock = (uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER) |
> -			((uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER) << 32ULL);
> +		clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER);
> +		clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER);
> +		hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER);
> +		// If carry happens, continuously read until no carry happens
> +		while (hi_check != clock_hi) {
> +			clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER);
> +			clock_hi = hi_check;
> +			hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER);
> +		}

This could be refined into:

do {
     clock_hi =READ_...
     clock_lo = READ_....
} while (unlikely(clock_hi != READ_....))

Apart from that looks like a good idea to me.

Regards,
Christian.

> +		clock = (uint64_t)clock_lo | ((uint64_t)clock_hi << 32ULL);
>   		break;
>   	}
>   	mutex_unlock(&adev->gfx.gpu_clock_mutex);