[PATCH] drm/amdgpu: Use correct size when access vram
Christian König
christian.koenig at amd.com
Mon Mar 22 07:55:14 UTC 2021
Am 22.03.21 um 01:53 schrieb xinhui pan:
> To make size is 4 byte aligned. Use &~0x3ULL instead of &3ULL.
>
> Signed-off-by: xinhui pan <xinhui.pan at amd.com>
Good catch. Patch is Reviewed-by: Christian König <christian.koenig at amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> index 6d5cf0525325..41a4c456961c 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> @@ -1503,7 +1503,7 @@ static int amdgpu_ttm_access_memory(struct ttm_buffer_object *bo,
> memcpy(buf, &value, bytes);
> }
> } else {
> - bytes = cursor.size & 0x3ull;
> + bytes = cursor.size & ~0x3ULL;
> amdgpu_device_vram_access(adev, cursor.start,
> (uint32_t *)buf, bytes,
> write);
More information about the amd-gfx
mailing list