[PATCH] drm/amdgpu: seperate the dependency between CGCG and CGLS when diable CGCG/CGLS

Huang Rui ray.huang at amd.com
Tue May 11 04:22:04 UTC 2021 

On Thu, Apr 29, 2021 at 02:08:53PM +0800, Zhu, Changfeng wrote:
> From: changzhu <Changfeng.Zhu at amd.com>
> 
> From: Changfeng <Changfeng.Zhu at amd.com>
> 
> The disable process of CGLS is dependent on CGCG now. Align with windows
> code, seperate the dependency between CGCG and CGLS and it will reduce
> confusion when debug CGCG/CGLS related issue.
> 
> Change-Id: Ia91b8b16236bebd9224160672e500f6850dbc268
> Signed-off-by: Changfeng <Changfeng.Zhu at amd.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 24 ++++++++++++-------
>  drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c  | 33 ++++++++++++++++----------
>  2 files changed, 37 insertions(+), 20 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> index 49fd10a15707..3f8aa2fb974d 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> @@ -7717,18 +7717,22 @@ static void gfx_v10_0_update_3d_clock_gating(struct amdgpu_device *adev,
>  	uint32_t data, def;
>  
>  	/* Enable 3D CGCG/CGLS */
> -	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)) {
> +	if (enable) {
>  		/* write cmd to clear cgcg/cgls ov */
>  		def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
>  		/* unset CGCG override */
> -		data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK;
> +		if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)
> +			data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK;
>  		/* update CGCG and CGLS override bits */
>  		if (def != data)
>  			WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
>  		/* enable 3Dcgcg FSM(0x0000363f) */
>  		def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
> -		data = (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
> -			RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
> +		data = 0;

The data should be inited with register default value like this:

def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);

Then you can set the mask according to clock gating enabling flag.

We should handle it like this on the following codes as well. With those
fixed, patch is Reviewed-by: Huang Rui <ray.huang at amd.com>

> +
> +		if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)
> +			data |= (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
> +				RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
>  		if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS)
>  			data |= (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
>  				RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK;
> @@ -7758,10 +7762,11 @@ static void gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device *ade
>  {
>  	uint32_t def, data;
>  
> -	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
> +	if (enable) {
>  		def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
>  		/* unset CGCG override */
> -		data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK;
> +		if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)
> +			data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK;
>  		if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
>  			data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
>  		else
> @@ -7772,8 +7777,11 @@ static void gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device *ade
>  
>  		/* enable cgcg FSM(0x0000363F) */
>  		def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
> -		data = (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
> -			RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
> +		data = 0;
> +
> +		if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)
> +			data |= (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
> +				RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
>  		if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
>  			data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
>  				RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> index 16a3b279a9ef..f69129097f2e 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> @@ -4946,20 +4946,23 @@ static void gfx_v9_0_update_3d_clock_gating(struct amdgpu_device *adev,
>  	amdgpu_gfx_rlc_enter_safe_mode(adev);
>  
>  	/* Enable 3D CGCG/CGLS */
> -	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)) {
> +	if (enable) {
>  		/* write cmd to clear cgcg/cgls ov */
>  		def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
>  		/* unset CGCG override */
> -		data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK;
> +		if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)
> +			data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK;
>  		/* update CGCG and CGLS override bits */
>  		if (def != data)
>  			WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
>  
>  		/* enable 3Dcgcg FSM(0x0000363f) */
>  		def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
> +		data = 0;
>  
> -		data = (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
> -			RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
> +		if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)
> +			data |= (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
> +				RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
>  		if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS)
>  			data |= (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
>  				RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK;
> @@ -4993,10 +4996,12 @@ static void gfx_v9_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev
>  
>  	amdgpu_gfx_rlc_enter_safe_mode(adev);
>  
> -	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
> +	if (enable) {
>  		def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
>  		/* unset CGCG override */
> -		data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK;
> +		if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)
> +			data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK;
> +
>  		if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
>  			data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
>  		else
> @@ -5007,13 +5012,17 @@ static void gfx_v9_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev
>  
>  		/* enable cgcg FSM(0x0000363F) */
>  		def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
> +		data = 0;
> +
> +		if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) {
> +			if (adev->asic_type == CHIP_ARCTURUS)
> +				data |= (0x2000 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
> +					RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
> +			else
> +				data |= (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
> +					RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
> +		}
>  
> -		if (adev->asic_type == CHIP_ARCTURUS)
> -			data = (0x2000 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
> -				RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
> -		else
> -			data = (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
> -				RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
>  		if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
>  			data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
>  				RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
> -- 
> 2.17.1
>

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