[PATCH v4 16/16] drm/amdgpu: Update gfx_v9 rlcg interface

[Zhou, Peng Ju]

[AMD Official Use Only - Internal Distribution Only]

Hi Felix/Christian
As we discussed before, we should access GC registers by RLCG by default in full access time.
Using RLCG interface if needed when access other IPs' registers.

The patches in the below(have been sent out) are the implementation of this proposal,
Can you help to review it?

The patches:
Subject: [PATCH v4 01/16] drm/amdgpu: Indirect register access for Navi12 sriov - new internal macro
Subject: [PATCH v4 02/16] drm/amdgpu: Indirect register access for Navi12 sriov - SOC15 macro
Subject: [PATCH v4 03/16] drm/amdgpu: Indirect register access for Navi12 sriov - RLC interface
Subject: [PATCH v4 04/16] drm/amdgpu: Indirect register access for Navi12 sriov - GFX v10
Subject: [PATCH v4 05/16] drm/amdgpu: Modify GC register access from MMIO to RLCG in file gfx_v10*
Subject: [PATCH v4 06/16] drm/amdgpu: Modify GC register access from MMIO to RLCG in file kfd_v10*
Subject: [PATCH v4 07/16] drm/amdgpu: Modify GC register access from MMIO to RLCG in file soc15.c
Subject: [PATCH v4 08/16] drm/amdgpu: Modify GC register access from MMIO to RLCG in file sdma_v5*
Subject: [PATCH v4 09/16] drm/amdgpu: Modify GC register access from MMIO to RLCG in file nv.c
Subject: [PATCH v4 10/16] drm/amdgpu: Modify GC register access from MMIO to RLCG in file amdgpu_gmc.c
Subject: [PATCH v4 11/16] drm/amdgpu: Modify MMHUB register access from MMIO to RLCG in file mmhub_v2*
Subject: [PATCH v4 12/16] drm/amdgpu: Use PSP to program IH_RB_CNTL* registers
Subject: [PATCH v4 13/16] drm/amdgpu: Skip the program of MMMC_VM_AGP_* in SRIOV
Subject: [PATCH v4 14/16] drm/amdgpu: Skip the program of GRBM_CAM* in SRIOV
Subject: [PATCH v4 15/16] drm/amdgpu: Refine the error report when flush tlb.
Subject: [PATCH v4 16/16] drm/amdgpu: Update gfx_v9 rlcg interface


---------------------------------------------------------------------- 
BW
Pengju Zhou




> -----Original Message-----
> From: Peng Ju Zhou <PengJu.Zhou at amd.com>
> Sent: Friday, May 14, 2021 3:27 PM
> To: amd-gfx at lists.freedesktop.org
> Cc: Zhou, Peng Ju <PengJu.Zhou at amd.com>
> Subject: [PATCH v4 16/16] drm/amdgpu: Update gfx_v9 rlcg interface
> 
> the interface on gfx v10 updated, the gfx v9 and v10 share the same interface,
> update v9's interface.
> 
> Signed-off-by: Peng Ju Zhou <PengJu.Zhou at amd.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 +-
>  drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c      | 9 +++++----
>  2 files changed, 6 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index 357f9405f1aa..ce7f9d01083b 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -490,7 +490,7 @@ void amdgpu_mm_wreg_mmio_rlc(struct
> amdgpu_device *adev,
>  	    adev->gfx.rlc.funcs &&
>  	    adev->gfx.rlc.funcs->is_rlcg_access_range) {
>  		if (adev->gfx.rlc.funcs->is_rlcg_access_range(adev, reg))
> -			return adev->gfx.rlc.funcs->rlcg_wreg(adev, reg, v, 0);
> +			return adev->gfx.rlc.funcs->rlcg_wreg(adev, reg, v, 0,
> 0);
>  	} else {
>  		writel(v, ((void __iomem *)adev->rmmio) + (reg * 4));
>  	}
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> index 16a3b279a9ef..59f3d8f922cd 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> @@ -734,7 +734,7 @@ static const u32
> GFX_RLC_SRM_INDEX_CNTL_DATA_OFFSETS[] =
>  	mmRLC_SRM_INDEX_CNTL_DATA_7 -
> mmRLC_SRM_INDEX_CNTL_DATA_0,  };
> 
> -static void gfx_v9_0_rlcg_rw(struct amdgpu_device *adev, u32 offset, u32 v,
> u32 flag)
> +static void gfx_v9_0_rlcg_w(struct amdgpu_device *adev, u32 offset, u32
> +v, u32 flag)
>  {
>  	static void *scratch_reg0;
>  	static void *scratch_reg1;
> @@ -787,15 +787,16 @@ static void gfx_v9_0_rlcg_rw(struct amdgpu_device
> *adev, u32 offset, u32 v, u32
> 
>  }
> 
> -static void gfx_v9_0_rlcg_wreg(struct amdgpu_device *adev, u32 offset, u32
> v, u32 flag)
> +static void gfx_v9_0_rlcg_wreg(struct amdgpu_device *adev, u32 offset,
> +			       u32 v, u32 acc_flags, u32 hwip)
>  {
>  	if (amdgpu_sriov_fullaccess(adev)) {
> -		gfx_v9_0_rlcg_rw(adev, offset, v, flag);
> +		gfx_v9_0_rlcg_w(adev, offset, v, acc_flags);
> 
>  		return;
>  	}
> 
> -	if (flag & AMDGPU_REGS_NO_KIQ)
> +	if (acc_flags & AMDGPU_REGS_NO_KIQ)
>  		WREG32_NO_KIQ(offset, v);
>  	else
>  		WREG32(offset, v);
> --
> 2.17.1