[PATCH v4 16/16] drm/amdgpu: Update gfx_v9 rlcg interface

[Alex Deucher]

On Fri, May 14, 2021 at 3:27 AM Peng Ju Zhou <PengJu.Zhou at amd.com> wrote:
>
> the interface on gfx v10 updated, the gfx v9 and v10
> share the same interface, update v9's interface.
>
> Signed-off-by: Peng Ju Zhou <PengJu.Zhou at amd.com>

This should be squashed with patch 4 to avoid a build breakage.

> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 +-
>  drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c      | 9 +++++----
>  2 files changed, 6 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index 357f9405f1aa..ce7f9d01083b 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -490,7 +490,7 @@ void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev,
>             adev->gfx.rlc.funcs &&
>             adev->gfx.rlc.funcs->is_rlcg_access_range) {
>                 if (adev->gfx.rlc.funcs->is_rlcg_access_range(adev, reg))
> -                       return adev->gfx.rlc.funcs->rlcg_wreg(adev, reg, v, 0);
> +                       return adev->gfx.rlc.funcs->rlcg_wreg(adev, reg, v, 0, 0);
>         } else {
>                 writel(v, ((void __iomem *)adev->rmmio) + (reg * 4));
>         }
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> index 16a3b279a9ef..59f3d8f922cd 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> @@ -734,7 +734,7 @@ static const u32 GFX_RLC_SRM_INDEX_CNTL_DATA_OFFSETS[] =
>         mmRLC_SRM_INDEX_CNTL_DATA_7 - mmRLC_SRM_INDEX_CNTL_DATA_0,
>  };
>
> -static void gfx_v9_0_rlcg_rw(struct amdgpu_device *adev, u32 offset, u32 v, u32 flag)
> +static void gfx_v9_0_rlcg_w(struct amdgpu_device *adev, u32 offset, u32 v, u32 flag)
>  {
>         static void *scratch_reg0;
>         static void *scratch_reg1;
> @@ -787,15 +787,16 @@ static void gfx_v9_0_rlcg_rw(struct amdgpu_device *adev, u32 offset, u32 v, u32
>
>  }
>
> -static void gfx_v9_0_rlcg_wreg(struct amdgpu_device *adev, u32 offset, u32 v, u32 flag)
> +static void gfx_v9_0_rlcg_wreg(struct amdgpu_device *adev, u32 offset,
> +                              u32 v, u32 acc_flags, u32 hwip)
>  {
>         if (amdgpu_sriov_fullaccess(adev)) {
> -               gfx_v9_0_rlcg_rw(adev, offset, v, flag);
> +               gfx_v9_0_rlcg_w(adev, offset, v, acc_flags);
>
>                 return;
>         }
>
> -       if (flag & AMDGPU_REGS_NO_KIQ)
> +       if (acc_flags & AMDGPU_REGS_NO_KIQ)
>                 WREG32_NO_KIQ(offset, v);
>         else
>                 WREG32(offset, v);
> --
> 2.17.1
>
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