[PATCH] drm/amd/display: Correct MPC split policy for DCN301

Liu, Charlene Charlene.Liu at amd.com
Thu Jan 20 02:20:20 UTC 2022

[AMD Official Use Only]

-----Original Message-----
From: Liu, Zhan <Zhan.Liu at amd.com> 
Sent: Wednesday, January 19, 2022 5:17 PM
To: amd-gfx at lists.freedesktop.org
Cc: Liu, Charlene <Charlene.Liu at amd.com>; Cornij, Nikola <Nikola.Cornij at amd.com>; Gutierrez, Agustin <Agustin.Gutierrez at amd.com>; Pierre-Loup Griffais <pgriffais at valvesoftware.com>; Kotarac, Pavle <Pavle.Kotarac at amd.com>
Subject: [PATCH] drm/amd/display: Correct MPC split policy for DCN301

[AMD Official Use Only]

DCN301 has seamless boot enabled. With MPC split enabled at the same time, system will hang.

Revert MPC split policy back to "MPC_SPLIT_AVOID". Since we have ODM combine enabled on DCN301, pipe split is not necessary here.

Signed-off-by: Zhan Liu <zhan.liu at amd.com>
Reviewed-by: Charlene Liu <charlene.liu at amd.com>
 drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c
index c1c6e602b06c..b4001233867c 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_resource.c
@@ -686,7 +686,7 @@ static const struct dc_debug_options debug_defaults_drv = {
        .disable_clock_gate = true,
        .disable_pplib_clock_request = true,
        .disable_pplib_wm_range = true,
-       .pipe_split_policy = MPC_SPLIT_DYNAMIC,
+       .pipe_split_policy = MPC_SPLIT_AVOID,
        .force_single_disp_pipe_split = false,
        .disable_dcc = DCC_ENABLE,
        .vsr_support = true,

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