[PATCH] drm/amdgpu: Stop clearing kiq position during unload

[Luben Tuikov]

On 2022-11-10 03:42, YuBiao Wang wrote:
> Do not clear kiq position in RLC_CP_SCHEDULER so that CP could perform
> IDLE-SAVE after VF fini. CPG also needs to be active in save command.
> 
> Signed-off-by: YuBiao Wang <YuBiao.Wang at amd.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 14 ++++++--------
>  drivers/gpu/drm/amd/amdgpu/mes_v11_0.c |  4 +++-
>  2 files changed, 9 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
> index 9447999a3a48..232ccd639184 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
> @@ -4411,15 +4411,13 @@ static int gfx_v11_0_hw_fini(void *handle)
>  		amdgpu_mes_kiq_hw_fini(adev);
>  	}
>  
> -	if (amdgpu_sriov_vf(adev)) {
> -		gfx_v11_0_cp_gfx_enable(adev, false);
> -		/* Program KIQ position of RLC_CP_SCHEDULERS during destroy */
> -		tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS);
> -		tmp &= 0xffffff00;
> -		WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp);
> -
> +	if (amdgpu_sriov_vf(adev))
> +		/* Remove the steps disabling CPG and clearing KIQ position,
> +		 * so that CP could perform IDLE-SAVE during switch.
> +		 * Those steps were to avoid a DMAR error in gfx9 but it is not reproduced on gfx11.
> +		 */
>  		return 0;
> -	}

Wrap this comment to the 80-char limit. If you're using Emacs,
set the pointer (cursor) anywhere in the comment, then
the following key sequence, C-u 78 C-x f M-q, reformats the comment
to look like this:

		/* Remove the steps disabling CPG and clearing KIQ position,
		 * so that CP could perform IDLE-SAVE during switch. Those
		 * steps are necessary to avoid a DMAR error in gfx9 but it is
		 * not reproduced on gfx11.
		 */

>From then on, you can just press M-q anywhere as often as you'd like
for format anything.

Also note the change from "Those steps were to avoid ..." to "Those steps
are necessary to avoid ...".

With that fixed, this patch is,

Reviewed-by: Luben Tuikov <luben.tuikov at amd.com>

Regards,
Luben

> +
>  	gfx_v11_0_cp_enable(adev, false);
>  	gfx_v11_0_enable_gui_idle_interrupt(adev, false);
>  
> diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
> index 7bfe862aa83e..02ad84a1526a 100644
> --- a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c
> @@ -1248,7 +1248,9 @@ static int mes_v11_0_kiq_hw_fini(struct amdgpu_device *adev)
>  	if (adev->mes.ring.sched.ready)
>  		mes_v11_0_kiq_dequeue_sched(adev);
>  
> -	mes_v11_0_enable(adev, false);
> +	if (!amdgpu_sriov_vf(adev))
> +		mes_v11_0_enable(adev, false);
> +
>  	return 0;
>  }
>