[PATCH 09/10] drm/amdgpu/gfx10: switch to amdgpu_gfx_rlc_init_microcode

Zhang, Hawking Hawking.Zhang at amd.com
Sat Sep 24 07:14:58 UTC 2022


[Public]

Hi Alex,

Sienna cichlid rlc firmware binary needs to be updated to match with the kernel change.

I shall add this comment to commit description.

Regards,
Hawking

From: Deucher, Alexander <Alexander.Deucher at amd.com>
Sent: Saturday, September 24, 2022 05:36
To: Zhang, Hawking <Hawking.Zhang at amd.com>; amd-gfx at lists.freedesktop.org; Gao, Likun <Likun.Gao at amd.com>
Subject: Re: [PATCH 09/10] drm/amdgpu/gfx10: switch to amdgpu_gfx_rlc_init_microcode


[Public]

This set seems to break RLC firmware loading on sienna cichlid.

Alex
________________________________
From: Zhang, Hawking <Hawking.Zhang at amd.com<mailto:Hawking.Zhang at amd.com>>
Sent: Thursday, September 15, 2022 1:01 PM
To: amd-gfx at lists.freedesktop.org<mailto:amd-gfx at lists.freedesktop.org> <amd-gfx at lists.freedesktop.org<mailto:amd-gfx at lists.freedesktop.org>>; Gao, Likun <Likun.Gao at amd.com<mailto:Likun.Gao at amd.com>>; Deucher, Alexander <Alexander.Deucher at amd.com<mailto:Alexander.Deucher at amd.com>>
Cc: Zhang, Hawking <Hawking.Zhang at amd.com<mailto:Hawking.Zhang at amd.com>>
Subject: [PATCH 09/10] drm/amdgpu/gfx10: switch to amdgpu_gfx_rlc_init_microcode

switch to common helper to initialize rlc firmware
for gfx10

Signed-off-by: Hawking Zhang <Hawking.Zhang at amd.com<mailto:Hawking.Zhang at amd.com>>
---
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 191 +------------------------
 1 file changed, 4 insertions(+), 187 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 26ec04fd313b..423b1b6d31b6 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -3943,56 +3943,6 @@ static void gfx_v10_0_check_fw_write_wait(struct amdgpu_device *adev)
                 DRM_WARN_ONCE("CP firmware version too old, please update!");
 }

-
-static void gfx_v10_0_init_rlc_ext_microcode(struct amdgpu_device *adev)
-{
-       const struct rlc_firmware_header_v2_1 *rlc_hdr;
-
-       rlc_hdr = (const struct rlc_firmware_header_v2_1 *)adev->gfx.rlc_fw->data;
-       adev->gfx.rlc_srlc_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_ucode_ver);
-       adev->gfx.rlc_srlc_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_feature_ver);
-       adev->gfx.rlc.save_restore_list_cntl_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_cntl_size_bytes);
-       adev->gfx.rlc.save_restore_list_cntl = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_cntl_offset_bytes);
-       adev->gfx.rlc_srlg_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_ucode_ver);
-       adev->gfx.rlc_srlg_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_feature_ver);
-       adev->gfx.rlc.save_restore_list_gpm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_gpm_size_bytes);
-       adev->gfx.rlc.save_restore_list_gpm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_gpm_offset_bytes);
-       adev->gfx.rlc_srls_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_ucode_ver);
-       adev->gfx.rlc_srls_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_feature_ver);
-       adev->gfx.rlc.save_restore_list_srm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_srm_size_bytes);
-       adev->gfx.rlc.save_restore_list_srm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_srm_offset_bytes);
-       adev->gfx.rlc.reg_list_format_direct_reg_list_length =
-                       le32_to_cpu(rlc_hdr->reg_list_format_direct_reg_list_length);
-}
-
-static void gfx_v10_0_init_rlc_iram_dram_microcode(struct amdgpu_device *adev)
-{
-       const struct rlc_firmware_header_v2_2 *rlc_hdr;
-
-       rlc_hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data;
-       adev->gfx.rlc.rlc_iram_ucode_size_bytes = le32_to_cpu(rlc_hdr->rlc_iram_ucode_size_bytes);
-       adev->gfx.rlc.rlc_iram_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->rlc_iram_ucode_offset_bytes);
-       adev->gfx.rlc.rlc_dram_ucode_size_bytes = le32_to_cpu(rlc_hdr->rlc_dram_ucode_size_bytes);
-       adev->gfx.rlc.rlc_dram_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->rlc_dram_ucode_offset_bytes);
-}
-
-static void gfx_v10_0_init_tap_delays_microcode(struct amdgpu_device *adev)
-{
-       const struct rlc_firmware_header_v2_4 *rlc_hdr;
-
-       rlc_hdr = (const struct rlc_firmware_header_v2_4 *)adev->gfx.rlc_fw->data;
-       adev->gfx.rlc.global_tap_delays_ucode_size_bytes = le32_to_cpu(rlc_hdr->global_tap_delays_ucode_size_bytes);
-       adev->gfx.rlc.global_tap_delays_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->global_tap_delays_ucode_offset_bytes);
-       adev->gfx.rlc.se0_tap_delays_ucode_size_bytes = le32_to_cpu(rlc_hdr->se0_tap_delays_ucode_size_bytes);
-       adev->gfx.rlc.se0_tap_delays_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->se0_tap_delays_ucode_offset_bytes);
-       adev->gfx.rlc.se1_tap_delays_ucode_size_bytes = le32_to_cpu(rlc_hdr->se1_tap_delays_ucode_size_bytes);
-       adev->gfx.rlc.se1_tap_delays_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->se1_tap_delays_ucode_offset_bytes);
-       adev->gfx.rlc.se2_tap_delays_ucode_size_bytes = le32_to_cpu(rlc_hdr->se2_tap_delays_ucode_size_bytes);
-       adev->gfx.rlc.se2_tap_delays_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->se2_tap_delays_ucode_offset_bytes);
-       adev->gfx.rlc.se3_tap_delays_ucode_size_bytes = le32_to_cpu(rlc_hdr->se3_tap_delays_ucode_size_bytes);
-       adev->gfx.rlc.se3_tap_delays_ucode = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->se3_tap_delays_ucode_offset_bytes);
-}
-
 static bool gfx_v10_0_navi10_gfxoff_should_enable(struct amdgpu_device *adev)
 {
         bool ret = false;
@@ -4032,8 +3982,6 @@ static int gfx_v10_0_init_microcode(struct amdgpu_device *adev)
         const struct common_firmware_header *header = NULL;
         const struct gfx_firmware_header_v1_0 *cp_hdr;
         const struct rlc_firmware_header_v2_0 *rlc_hdr;
-       unsigned int *tmp = NULL;
-       unsigned int i = 0;
         uint16_t version_major;
         uint16_t version_minor;

@@ -4123,59 +4071,14 @@ static int gfx_v10_0_init_microcode(struct amdgpu_device *adev)
                 if (err)
                         goto out;
                 err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
+               if (err)
+                       goto out;
                 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
                 version_major = le16_to_cpu(rlc_hdr->header.header_version_major);
                 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor);
-
-               adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version);
-               adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version);
-               adev->gfx.rlc.save_and_restore_offset =
-                       le32_to_cpu(rlc_hdr->save_and_restore_offset);
-               adev->gfx.rlc.clear_state_descriptor_offset =
-                       le32_to_cpu(rlc_hdr->clear_state_descriptor_offset);
-               adev->gfx.rlc.avail_scratch_ram_locations =
-                       le32_to_cpu(rlc_hdr->avail_scratch_ram_locations);
-               adev->gfx.rlc.reg_restore_list_size =
-                       le32_to_cpu(rlc_hdr->reg_restore_list_size);
-               adev->gfx.rlc.reg_list_format_start =
-                       le32_to_cpu(rlc_hdr->reg_list_format_start);
-               adev->gfx.rlc.reg_list_format_separate_start =
-                       le32_to_cpu(rlc_hdr->reg_list_format_separate_start);
-               adev->gfx.rlc.starting_offsets_start =
-                       le32_to_cpu(rlc_hdr->starting_offsets_start);
-               adev->gfx.rlc.reg_list_format_size_bytes =
-                       le32_to_cpu(rlc_hdr->reg_list_format_size_bytes);
-               adev->gfx.rlc.reg_list_size_bytes =
-                       le32_to_cpu(rlc_hdr->reg_list_size_bytes);
-               adev->gfx.rlc.register_list_format =
-                       kmalloc(adev->gfx.rlc.reg_list_format_size_bytes +
-                                       adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL);
-               if (!adev->gfx.rlc.register_list_format) {
-                       err = -ENOMEM;
+               err = amdgpu_gfx_rlc_init_microcode(adev, version_major, version_minor);
+               if (err)
                         goto out;
-               }
-
-               tmp = (unsigned int *)((uintptr_t)rlc_hdr +
-                                                          le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes));
-               for (i = 0 ; i < (rlc_hdr->reg_list_format_size_bytes >> 2); i++)
-                       adev->gfx.rlc.register_list_format[i] = le32_to_cpu(tmp[i]);
-
-               adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i;
-
-               tmp = (unsigned int *)((uintptr_t)rlc_hdr +
-                                                          le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes));
-               for (i = 0 ; i < (rlc_hdr->reg_list_size_bytes >> 2); i++)
-                       adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]);
-
-               if (version_major == 2) {
-                       if (version_minor >= 1)
-                               gfx_v10_0_init_rlc_ext_microcode(adev);
-                       if (version_minor >= 2)
-                               gfx_v10_0_init_rlc_iram_dram_microcode(adev);
-                       if (version_minor == 4) {
-                               gfx_v10_0_init_tap_delays_microcode(adev);
-                       }
-               }
         }

         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec%s.bin", chip_name, wks);
@@ -4228,92 +4131,6 @@ static int gfx_v10_0_init_microcode(struct amdgpu_device *adev)
                 adev->firmware.fw_size +=
                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);

-               info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G];
-               info->ucode_id = AMDGPU_UCODE_ID_RLC_G;
-               info->fw = adev->gfx.rlc_fw;
-               if (info->fw) {
-                       header = (const struct common_firmware_header *)info->fw->data;
-                       adev->firmware.fw_size +=
-                               ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
-               }
-               if (adev->gfx.rlc.save_restore_list_cntl_size_bytes &&
-                   adev->gfx.rlc.save_restore_list_gpm_size_bytes &&
-                   adev->gfx.rlc.save_restore_list_srm_size_bytes) {
-                       info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL];
-                       info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL;
-                       info->fw = adev->gfx.rlc_fw;
-                       adev->firmware.fw_size +=
-                               ALIGN(adev->gfx.rlc.save_restore_list_cntl_size_bytes, PAGE_SIZE);
-
-                       info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM];
-                       info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM;
-                       info->fw = adev->gfx.rlc_fw;
-                       adev->firmware.fw_size +=
-                               ALIGN(adev->gfx.rlc.save_restore_list_gpm_size_bytes, PAGE_SIZE);
-
-                       info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM];
-                       info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM;
-                       info->fw = adev->gfx.rlc_fw;
-                       adev->firmware.fw_size +=
-                               ALIGN(adev->gfx.rlc.save_restore_list_srm_size_bytes, PAGE_SIZE);
-
-                       if (adev->gfx.rlc.rlc_iram_ucode_size_bytes &&
-                           adev->gfx.rlc.rlc_dram_ucode_size_bytes) {
-                               info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_IRAM];
-                               info->ucode_id = AMDGPU_UCODE_ID_RLC_IRAM;
-                               info->fw = adev->gfx.rlc_fw;
-                               adev->firmware.fw_size +=
-                                       ALIGN(adev->gfx.rlc.rlc_iram_ucode_size_bytes, PAGE_SIZE);
-
-                               info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_DRAM];
-                               info->ucode_id = AMDGPU_UCODE_ID_RLC_DRAM;
-                               info->fw = adev->gfx.rlc_fw;
-                               adev->firmware.fw_size +=
-                                       ALIGN(adev->gfx.rlc.rlc_dram_ucode_size_bytes, PAGE_SIZE);
-                       }
-
-               }
-
-               if (adev->gfx.rlc.global_tap_delays_ucode_size_bytes) {
-                       info = &adev->firmware.ucode[AMDGPU_UCODE_ID_GLOBAL_TAP_DELAYS];
-                       info->ucode_id = AMDGPU_UCODE_ID_GLOBAL_TAP_DELAYS;
-                       info->fw = adev->gfx.rlc_fw;
-                       adev->firmware.fw_size +=
-                               ALIGN(adev->gfx.rlc.global_tap_delays_ucode_size_bytes, PAGE_SIZE);
-               }
-
-               if (adev->gfx.rlc.se0_tap_delays_ucode_size_bytes) {
-                       info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SE0_TAP_DELAYS];
-                       info->ucode_id = AMDGPU_UCODE_ID_SE0_TAP_DELAYS;
-                       info->fw = adev->gfx.rlc_fw;
-                       adev->firmware.fw_size +=
-                               ALIGN(adev->gfx.rlc.se0_tap_delays_ucode_size_bytes, PAGE_SIZE);
-               }
-
-               if (adev->gfx.rlc.se1_tap_delays_ucode_size_bytes) {
-                       info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SE1_TAP_DELAYS];
-                       info->ucode_id = AMDGPU_UCODE_ID_SE1_TAP_DELAYS;
-                       info->fw = adev->gfx.rlc_fw;
-                       adev->firmware.fw_size +=
-                               ALIGN(adev->gfx.rlc.se1_tap_delays_ucode_size_bytes, PAGE_SIZE);
-               }
-
-               if (adev->gfx.rlc.se2_tap_delays_ucode_size_bytes) {
-                       info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SE2_TAP_DELAYS];
-                       info->ucode_id = AMDGPU_UCODE_ID_SE2_TAP_DELAYS;
-                       info->fw = adev->gfx.rlc_fw;
-                       adev->firmware.fw_size +=
-                               ALIGN(adev->gfx.rlc.se2_tap_delays_ucode_size_bytes, PAGE_SIZE);
-               }
-
-               if (adev->gfx.rlc.se3_tap_delays_ucode_size_bytes) {
-                       info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SE3_TAP_DELAYS];
-                       info->ucode_id = AMDGPU_UCODE_ID_SE3_TAP_DELAYS;
-                       info->fw = adev->gfx.rlc_fw;
-                       adev->firmware.fw_size +=
-                               ALIGN(adev->gfx.rlc.se3_tap_delays_ucode_size_bytes, PAGE_SIZE);
-               }
-
                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1];
                 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1;
                 info->fw = adev->gfx.mec_fw;
--
2.17.1
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