[bug report] drm/amdgpu/gfx11: add aggregated doorbell support
Dan Carpenter
dan.carpenter at linaro.org
Tue Jul 11 06:59:51 UTC 2023
Hello Jack Xiao,
The patch af019bef6d6f: "drm/amdgpu/gfx11: add aggregated doorbell
support" from Jul 11, 2022, leads to the following Smatch static
checker warning:
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c:5193 gfx_v11_0_ring_set_wptr_gfx()
warn: duplicate check '*is_queue_unmap'
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
5166 static void gfx_v11_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
5167 {
5168 struct amdgpu_device *adev = ring->adev;
5169 uint32_t *wptr_saved;
5170 uint32_t *is_queue_unmap;
5171 uint64_t aggregated_db_index;
5172 uint32_t mqd_size = adev->mqds[AMDGPU_HW_IP_GFX].mqd_size;
5173 uint64_t wptr_tmp;
5174
5175 if (ring->is_mes_queue) {
5176 wptr_saved = (uint32_t *)(ring->mqd_ptr + mqd_size);
5177 is_queue_unmap = (uint32_t *)(ring->mqd_ptr + mqd_size +
5178 sizeof(uint32_t));
5179 aggregated_db_index =
5180 amdgpu_mes_get_aggregated_doorbell_index(adev,
5181 ring->hw_prio);
5182
5183 wptr_tmp = ring->wptr & ring->buf_mask;
5184 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, wptr_tmp);
5185 *wptr_saved = wptr_tmp;
5186 /* assume doorbell always being used by mes mapped queue */
5187 if (*is_queue_unmap) {
^^^^^^^^^^^^^^^
Non-zero here.
5188 WDOORBELL64(aggregated_db_index, wptr_tmp);
5189 WDOORBELL64(ring->doorbell_index, wptr_tmp);
5190 } else {
5191 WDOORBELL64(ring->doorbell_index, wptr_tmp);
5192
--> 5193 if (*is_queue_unmap)
^^^^^^^^^^^^^^^
You would think it's zero here. Although, possibly this value is
getting set in another thread?
5194 WDOORBELL64(aggregated_db_index, wptr_tmp);
5195 }
5196 } else {
5197 if (ring->use_doorbell) {
5198 /* XXX check if swapping is necessary on BE */
5199 atomic64_set((atomic64_t *)ring->wptr_cpu_addr,
5200 ring->wptr);
5201 WDOORBELL64(ring->doorbell_index, ring->wptr);
5202 } else {
5203 WREG32_SOC15(GC, 0, regCP_RB0_WPTR,
5204 lower_32_bits(ring->wptr));
5205 WREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI,
5206 upper_32_bits(ring->wptr));
5207 }
5208 }
5209 }
regards,
dan carpenter
More information about the amd-gfx
mailing list