[PATCH] drm/amd: Fix initialization mistake for NBIO 7.3.0

[Alex Deucher]

On Thu, Mar 2, 2023 at 12:28 PM Mario Limonciello
<mario.limonciello at amd.com> wrote:
>
> The same strapping initialization issue that happened on NBIO 7.5.1
> appears to be happening on NBIO 7.3.0.
> Apply the same fix to 7.3.0 as well.
>
> Note: This workaround relies upon the integrated GPU being enabled
> in BIOS. If the integrated GPU is disabled in BIOS a different
> workaround will be required.
>
> Reported-by: Thomas Glanzmann <thomas at glanzmann.de>
> Cc: Basavaraj Natikar <Basavaraj.Natikar at amd.com>
> Link: https://lore.kernel.org/linux-usb/Y%2Fz9GdHjPyF2rNG3@glanzmann.de/T/#u
> Signed-off-by: Mario Limonciello <mario.limonciello at amd.com>

Reviewed-by: Alex Deucher <alexander.deucher at amd.com>

> ---
>  drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c | 14 +++++++++-----
>  1 file changed, 9 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c
> index 4b0d563c6522c..4ef1fa4603c8e 100644
> --- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c
> +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c
> @@ -382,11 +382,6 @@ static void nbio_v7_2_init_registers(struct amdgpu_device *adev)
>                 if (def != data)
>                         WREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regBIF1_PCIE_MST_CTRL_3), data);
>                 break;
> -       case IP_VERSION(7, 5, 1):
> -               data = RREG32_SOC15(NBIO, 0, regRCC_DEV2_EPF0_STRAP2);
> -               data &= ~RCC_DEV2_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV2_F0_MASK;
> -               WREG32_SOC15(NBIO, 0, regRCC_DEV2_EPF0_STRAP2, data);
> -               fallthrough;
>         default:
>                 def = data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CONFIG_CNTL));
>                 data = REG_SET_FIELD(data, PCIE_CONFIG_CNTL,
> @@ -399,6 +394,15 @@ static void nbio_v7_2_init_registers(struct amdgpu_device *adev)
>                 break;
>         }
>
> +       switch (adev->ip_versions[NBIO_HWIP][0]) {
> +       case IP_VERSION(7, 3, 0):
> +       case IP_VERSION(7, 5, 1):
> +               data = RREG32_SOC15(NBIO, 0, regRCC_DEV2_EPF0_STRAP2);
> +               data &= ~RCC_DEV2_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV2_F0_MASK;
> +               WREG32_SOC15(NBIO, 0, regRCC_DEV2_EPF0_STRAP2, data);
> +               break;
> +       }
> +
>         if (amdgpu_sriov_vf(adev))
>                 adev->rmmio_remap.reg_offset = SOC15_REG_OFFSET(NBIO, 0,
>                         regBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL) << 2;
> --
> 2.25.1
>