[PATCH] drm/amd: Fix initialization mistake for NBIO 7.3.0

[Thomas Glanzmann]

Hello Mario,

* Mario Limonciello <mario.limonciello at amd.com> [2023-03-02 18:27]:
> The same strapping initialization issue that happened on NBIO 7.5.1
> appears to be happening on NBIO 7.3.0.
> Apply the same fix to 7.3.0 as well.

> Note: This workaround relies upon the integrated GPU being enabled
> in BIOS. If the integrated GPU is disabled in BIOS a different
> workaround will be required.

> Reported-by: Thomas Glanzmann <thomas at glanzmann.de>
> Cc: Basavaraj Natikar <Basavaraj.Natikar at amd.com>
> Link: https://lore.kernel.org/linux-usb/Y%2Fz9GdHjPyF2rNG3@glanzmann.de/T/#u
> Signed-off-by: Mario Limonciello <mario.limonciello at amd.com>

Tested-by: Thomas Glanzmann <thomas at glanzmann.de>

> ---
>  drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c | 14 +++++++++-----
>  1 file changed, 9 insertions(+), 5 deletions(-)

> diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c
> index 4b0d563c6522c..4ef1fa4603c8e 100644
> --- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c
> +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_2.c
> @@ -382,11 +382,6 @@ static void nbio_v7_2_init_registers(struct amdgpu_device *adev)
>  		if (def != data)
>  			WREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regBIF1_PCIE_MST_CTRL_3), data);
>  		break;
> -	case IP_VERSION(7, 5, 1):
> -		data = RREG32_SOC15(NBIO, 0, regRCC_DEV2_EPF0_STRAP2);
> -		data &= ~RCC_DEV2_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV2_F0_MASK;
> -		WREG32_SOC15(NBIO, 0, regRCC_DEV2_EPF0_STRAP2, data);
> -		fallthrough;
>  	default:
>  		def = data = RREG32_PCIE_PORT(SOC15_REG_OFFSET(NBIO, 0, regPCIE_CONFIG_CNTL));
>  		data = REG_SET_FIELD(data, PCIE_CONFIG_CNTL,
> @@ -399,6 +394,15 @@ static void nbio_v7_2_init_registers(struct amdgpu_device *adev)
>  		break;
>  	}

My tree did not have the above hunk, so I only applied the second hunk.

I replugged by mouse keyboard several times and I have no longer any
issues.

Find output of dmesg; lsusb; lspci; dmidecode; lscpu here:

https://tg.st/u/498cb495b307353870e4dbba901a9c7aa58b89d918f54fc73f014f9a4778cc2a.txt

> +	switch (adev->ip_versions[NBIO_HWIP][0]) {
> +	case IP_VERSION(7, 3, 0):
> +	case IP_VERSION(7, 5, 1):
> +		data = RREG32_SOC15(NBIO, 0, regRCC_DEV2_EPF0_STRAP2);
> +		data &= ~RCC_DEV2_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV2_F0_MASK;
> +		WREG32_SOC15(NBIO, 0, regRCC_DEV2_EPF0_STRAP2, data);
> +		break;
> +	}
> +
>  	if (amdgpu_sriov_vf(adev))
>  		adev->rmmio_remap.reg_offset = SOC15_REG_OFFSET(NBIO, 0,
>  			regBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL) << 2;

Thank you for the workaround.

Cheers,
        Thomas