[PATCH] drm/amdgpu: Force order between a read and write to the same address
Alex Deucher
alexdeucher at gmail.com
Mon Nov 20 18:51:07 UTC 2023
On Sat, Nov 18, 2023 at 1:12 PM Alex Sierra <alex.sierra at amd.com> wrote:
>
> Setting register to force ordering to prevent read/write or write/read
> hazards for un-cached modes.
>
> Signed-off-by: Alex Sierra <alex.sierra at amd.com>
Acked-by: Alex Deucher <alexander.deucher at amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 22 +++++++++++++------
> drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 8 +++++++
> .../include/asic_reg/gc/gc_11_0_0_offset.h | 2 ++
> 3 files changed, 25 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> index 68747a52e5c2..592ac993f013 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> @@ -3193,7 +3193,8 @@ static const struct soc15_reg_golden golden_settings_gc_10_3[] = {
> SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
> SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0x00010000, 0x00010020),
> SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
> - SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000)
> + SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000),
> + SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x20000000, 0x20000000)
> };
>
> static const struct soc15_reg_golden golden_settings_gc_10_3_sienna_cichlid[] = {
> @@ -3245,6 +3246,7 @@ static const struct soc15_reg_golden golden_settings_gc_10_3_2[] = {
>
> /* This is not in GDB yet. Don't remove it. It fixes a GPU hang on Navy Flounder. */
> SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x00000020, 0x00000020),
> + SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x20000000, 0x20000000)
> };
>
> static const struct soc15_reg_golden golden_settings_gc_10_3_vangogh[] = {
> @@ -3275,6 +3277,7 @@ static const struct soc15_reg_golden golden_settings_gc_10_3_vangogh[] = {
>
> /* This is not in GDB yet. Don't remove it. It fixes a GPU hang on VanGogh. */
> SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x00000020, 0x00000020),
> + SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x20000000, 0x20000000)
> };
>
> static const struct soc15_reg_golden golden_settings_gc_10_3_3[] = {
> @@ -3297,7 +3300,8 @@ static const struct soc15_reg_golden golden_settings_gc_10_3_3[] = {
> SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
> SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
> SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
> - SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00100000)
> + SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00100000),
> + SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x20000000, 0x20000000)
> };
>
> static const struct soc15_reg_golden golden_settings_gc_10_3_4[] = {
> @@ -3336,7 +3340,8 @@ static const struct soc15_reg_golden golden_settings_gc_10_3_4[] = {
> SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0x00010000, 0x00010020),
> SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0x01030000, 0x01030000),
> SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x03a00000, 0x00a00000),
> - SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x00000020, 0x00000020)
> + SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x00000020, 0x00000020),
> + SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x20000000, 0x20000000)
> };
>
> static const struct soc15_reg_golden golden_settings_gc_10_3_5[] = {
> @@ -3371,7 +3376,8 @@ static const struct soc15_reg_golden golden_settings_gc_10_3_5[] = {
> SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),
> SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
> SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
> - SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000)
> + SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000),
> + SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x20000000, 0x20000000)
> };
>
> static const struct soc15_reg_golden golden_settings_gc_10_0_cyan_skillfish[] = {
> @@ -3408,7 +3414,7 @@ static const struct soc15_reg_golden golden_settings_gc_10_0_cyan_skillfish[] =
> SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000100, 0x00000130),
> SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
> SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0x00030008, 0x01030000),
> - SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00800000, 0x00800000)
> + SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00800000, 0x00800000),
> };
>
> static const struct soc15_reg_golden golden_settings_gc_10_3_6[] = {
> @@ -3433,7 +3439,8 @@ static const struct soc15_reg_golden golden_settings_gc_10_3_6[] = {
> SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000),
> SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0xffffff7f, 0x00010020),
> SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
> - SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00100000)
> + SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00100000),
> + SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x20000000, 0x20000000)
> };
>
> static const struct soc15_reg_golden golden_settings_gc_10_3_7[] = {
> @@ -3458,7 +3465,8 @@ static const struct soc15_reg_golden golden_settings_gc_10_3_7[] = {
> SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000),
> SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0xffffff7f, 0x00010020),
> SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
> - SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00100000)
> + SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00100000),
> + SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x20000000, 0x20000000)
> };
>
> #define DEFAULT_SH_MEM_CONFIG \
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
> index fd22943685f7..84decd069875 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
> @@ -89,6 +89,10 @@ MODULE_FIRMWARE("amdgpu/gc_11_5_0_me.bin");
> MODULE_FIRMWARE("amdgpu/gc_11_5_0_mec.bin");
> MODULE_FIRMWARE("amdgpu/gc_11_5_0_rlc.bin");
>
> +static const struct soc15_reg_golden golden_settings_gc_11_0[] = {
> + SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CNTL, 0x20000000, 0x20000000)
> +};
> +
> static const struct soc15_reg_golden golden_settings_gc_11_0_1[] =
> {
> SOC15_REG_GOLDEN_VALUE(GC, 0, regCGTT_GS_NGG_CLK_CTRL, 0x9fff8fff, 0x00000010),
> @@ -303,6 +307,10 @@ static void gfx_v11_0_init_golden_registers(struct amdgpu_device *adev)
> default:
> break;
> }
> + soc15_program_register_sequence(adev,
> + golden_settings_gc_11_0,
> + (const u32)ARRAY_SIZE(golden_settings_gc_11_0));
> +
> }
>
> static void gfx_v11_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel,
> diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_0_offset.h
> index c92c4b83253f..4bff1ef8a9a6 100644
> --- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_0_offset.h
> +++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_0_offset.h
> @@ -6369,6 +6369,8 @@
> #define regTCP_INVALIDATE_BASE_IDX 1
> #define regTCP_STATUS 0x19a1
> #define regTCP_STATUS_BASE_IDX 1
> +#define regTCP_CNTL 0x19a2
> +#define regTCP_CNTL_BASE_IDX 1
> #define regTCP_CNTL2 0x19a3
> #define regTCP_CNTL2_BASE_IDX 1
> #define regTCP_DEBUG_INDEX 0x19a5
> --
> 2.32.0
>
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