[PATCH] drm/amdgpu: Force order between a read and write to the same address

[Felix Kuehling]

On 2023-11-20 12:41, Alex Sierra wrote:
> Setting register to force ordering to prevent read/write or write/read
> hazards for un-cached modes.
>
> Signed-off-by: Alex Sierra <alex.sierra at amd.com>

Reviewed-by: Felix Kuehling <Felix.Kuehling at amd.com>


> ---
>   drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c                    | 8 ++++++++
>   .../gpu/drm/amd/include/asic_reg/gc/gc_11_0_0_offset.h    | 2 ++
>   2 files changed, 10 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
> index 0c6133cc5e57..40ce12323164 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
> @@ -89,6 +89,10 @@ MODULE_FIRMWARE("amdgpu/gc_11_5_0_me.bin");
>   MODULE_FIRMWARE("amdgpu/gc_11_5_0_mec.bin");
>   MODULE_FIRMWARE("amdgpu/gc_11_5_0_rlc.bin");
>   
> +static const struct soc15_reg_golden golden_settings_gc_11_0[] = {
> +	SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CNTL, 0x20000000, 0x20000000)
> +};
> +
>   static const struct soc15_reg_golden golden_settings_gc_11_0_1[] =
>   {
>   	SOC15_REG_GOLDEN_VALUE(GC, 0, regCGTT_GS_NGG_CLK_CTRL, 0x9fff8fff, 0x00000010),
> @@ -304,6 +308,10 @@ static void gfx_v11_0_init_golden_registers(struct amdgpu_device *adev)
>   	default:
>   		break;
>   	}
> +	soc15_program_register_sequence(adev,
> +					golden_settings_gc_11_0,
> +					(const u32)ARRAY_SIZE(golden_settings_gc_11_0));
> +
>   }
>   
>   static void gfx_v11_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel,
> diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_0_offset.h
> index c92c4b83253f..4bff1ef8a9a6 100644
> --- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_0_offset.h
> +++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_0_offset.h
> @@ -6369,6 +6369,8 @@
>   #define regTCP_INVALIDATE_BASE_IDX                                                                      1
>   #define regTCP_STATUS                                                                                   0x19a1
>   #define regTCP_STATUS_BASE_IDX                                                                          1
> +#define regTCP_CNTL                                                                                     0x19a2
> +#define regTCP_CNTL_BASE_IDX                                                                            1
>   #define regTCP_CNTL2                                                                                    0x19a3
>   #define regTCP_CNTL2_BASE_IDX                                                                           1
>   #define regTCP_DEBUG_INDEX                                                                              0x19a5