[PATCH 38/43] drm/amd/display: Fix MPCC DTN logging

[Melissa Wen]

On 28/03/2024 16:50, Roman.Li at amd.com wrote:
> From: Eric Bernstein <eric.bernstein at amd.com>
>
> [Why]
> DTN only logs 'pipe_count' instances of MPCC.
> However in some cases there are different number of
> MPCC than DPP (pipe_count).
>
> [How]
> Add mpcc_count parameter to resource_pool and set it
> during pool construction and use it for DTN logging of
> MPCC state.
Should we do the same in dcn*_log_color_state() for the loop of 
`pool->mpx->funcs->read_mpcc_state()` there?

It affects the following files:
drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c

BR,

Melissa
>
> Signed-off-by: Eric Bernstein <eric.bernstein at amd.com>
> Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira at amd.com>
> Tested-by: Daniel Wheeler <daniel.wheeler at amd.com>
> ---
>   drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c
> index 9033b39e0e0c..c51b717e5622 100644
> --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c
> +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c
> @@ -392,7 +392,7 @@ static unsigned int dcn10_get_mpcc_states(struct dc *dc, char *pBuf, unsigned in
>   	remaining_buffer -= chars_printed;
>   	pBuf += chars_printed;
>   
> -	for (i = 0; i < pool->pipe_count; i++) {
> +	for (i = 0; i < pool->mpcc_count; i++) {
>   		struct mpcc_state s = {0};
>   
>   		pool->mpc->funcs->read_mpcc_state(pool->mpc, i, &s);