[PATCH 1/2] drm/amdkfd: hard-code cahceline for gc11

[Belanger, David]

Please fix typo in title line:
cahceline -> cacheline

And I suggest also changing:
gc11 -> GFX11 (for consistency with typical name used in comments)

With comment fixes, I approve the commit:

Reviewed-by: David Belanger <david.belanger at amd.com>


On 11/28/2024 11:17 AM, Harish Kasiviswanathan wrote:
> This information is not available in ip discovery table.
>
> Signed-off-by: Harish Kasiviswanathan <Harish.Kasiviswanathan at amd.com>
> ---
>   drivers/gpu/drm/amd/amdkfd/kfd_crat.c | 22 ++++++++++++++++++++--
>   1 file changed, 20 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
> index 723f1220e1cc..3ca95f54601e 100644
> --- a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c
> @@ -1423,6 +1423,7 @@ int kfd_parse_crat_table(void *crat_image, struct list_head *device_list,
>   
>   
>   static int kfd_fill_gpu_cache_info_from_gfx_config(struct kfd_dev *kdev,
> +						   bool cache_line_size_missing,
>   						   struct kfd_gpu_cache_info *pcache_info)
>   {
>   	struct amdgpu_device *adev = kdev->adev;
> @@ -1437,6 +1438,8 @@ static int kfd_fill_gpu_cache_info_from_gfx_config(struct kfd_dev *kdev,
>   					CRAT_CACHE_FLAGS_SIMD_CACHE);
>   		pcache_info[i].num_cu_shared = adev->gfx.config.gc_num_tcp_per_wpg / 2;
>   		pcache_info[i].cache_line_size = adev->gfx.config.gc_tcp_cache_line_size;
> +		if (cache_line_size_missing && !pcache_info[i].cache_line_size)
> +			pcache_info[i].cache_line_size = 128;
>   		i++;
>   	}
>   	/* Scalar L1 Instruction Cache per SQC */
> @@ -1449,6 +1452,8 @@ static int kfd_fill_gpu_cache_info_from_gfx_config(struct kfd_dev *kdev,
>   					CRAT_CACHE_FLAGS_SIMD_CACHE);
>   		pcache_info[i].num_cu_shared = adev->gfx.config.gc_num_sqc_per_wgp * 2;
>   		pcache_info[i].cache_line_size = adev->gfx.config.gc_instruction_cache_line_size;
> +		if (cache_line_size_missing && !pcache_info[i].cache_line_size)
> +			pcache_info[i].cache_line_size = 128;
>   		i++;
>   	}
>   	/* Scalar L1 Data Cache per SQC */
> @@ -1460,6 +1465,8 @@ static int kfd_fill_gpu_cache_info_from_gfx_config(struct kfd_dev *kdev,
>   					CRAT_CACHE_FLAGS_SIMD_CACHE);
>   		pcache_info[i].num_cu_shared = adev->gfx.config.gc_num_sqc_per_wgp * 2;
>   		pcache_info[i].cache_line_size = adev->gfx.config.gc_scalar_data_cache_line_size;
> +		if (cache_line_size_missing && !pcache_info[i].cache_line_size)
> +			pcache_info[i].cache_line_size = 64;
>   		i++;
>   	}
>   	/* GL1 Data Cache per SA */
> @@ -1472,7 +1479,8 @@ static int kfd_fill_gpu_cache_info_from_gfx_config(struct kfd_dev *kdev,
>   					CRAT_CACHE_FLAGS_DATA_CACHE |
>   					CRAT_CACHE_FLAGS_SIMD_CACHE);
>   		pcache_info[i].num_cu_shared = adev->gfx.config.max_cu_per_sh;
> -		pcache_info[i].cache_line_size = 0;
> +		if (cache_line_size_missing)
> +			pcache_info[i].cache_line_size = 128;
>   		i++;
>   	}
>   	/* L2 Data Cache per GPU (Total Tex Cache) */
> @@ -1484,6 +1492,8 @@ static int kfd_fill_gpu_cache_info_from_gfx_config(struct kfd_dev *kdev,
>   					CRAT_CACHE_FLAGS_SIMD_CACHE);
>   		pcache_info[i].num_cu_shared = adev->gfx.config.max_cu_per_sh;
>   		pcache_info[i].cache_line_size = adev->gfx.config.gc_tcc_cache_line_size;
> +		if (cache_line_size_missing && !pcache_info[i].cache_line_size)
> +			pcache_info[i].cache_line_size = 128;
>   		i++;
>   	}
>   	/* L3 Data Cache per GPU */
> @@ -1563,6 +1573,7 @@ static int kfd_fill_gpu_cache_info_from_gfx_config_v2(struct kfd_dev *kdev,
>   int kfd_get_gpu_cache_info(struct kfd_node *kdev, struct kfd_gpu_cache_info **pcache_info)
>   {
>   	int num_of_cache_types = 0;
> +	bool cache_line_size_missing = false;
>   
>   	switch (kdev->adev->asic_type) {
>   	case CHIP_KAVERI:
> @@ -1686,10 +1697,17 @@ int kfd_get_gpu_cache_info(struct kfd_node *kdev, struct kfd_gpu_cache_info **pc
>   		case IP_VERSION(11, 5, 0):
>   		case IP_VERSION(11, 5, 1):
>   		case IP_VERSION(11, 5, 2):
> +			/* Cacheline size not available in IP discovery for gc11.
> +			 * kfd_fill_gpu_cache_info_from_gfx_config to hard code it
> +			 */
> +			cache_line_size_missing = true;
> +			fallthrough;
>   		case IP_VERSION(12, 0, 0):
>   		case IP_VERSION(12, 0, 1):
>   			num_of_cache_types =
> -				kfd_fill_gpu_cache_info_from_gfx_config(kdev->kfd, *pcache_info);
> +				kfd_fill_gpu_cache_info_from_gfx_config(kdev->kfd,
> +									cache_line_size_missing,
> +									*pcache_info);
>   			break;
>   		default:
>   			*pcache_info = dummy_cache_info;