[PATCH 3/4] drm/amdgpu: Use correct SRIOV macro for gmc_v9_0_vm_fault_interrupt_state

[Luo, Zhigang]

[AMD Official Use Only - General]

Reviewed By Zhigang Luo <Zhigang.Luo at amd.com>

From: Lu, Victor Cheng Chi (Victor) <VictorChengChi.Lu at amd.com>
Sent: Friday, February 16, 2024 1:50 PM
To: Luo, Zhigang <Zhigang.Luo at amd.com>
Subject: Fw: [PATCH 3/4] drm/amdgpu: Use correct SRIOV macro for gmc_v9_0_vm_fault_interrupt_state


[AMD Official Use Only - General]


________________________________
From: Lu, Victor Cheng Chi (Victor) <VictorChengChi.Lu at amd.com<mailto:VictorChengChi.Lu at amd.com>>
Sent: Tuesday, January 2, 2024 12:30 PM
To: amd-gfx at lists.freedesktop.org<mailto:amd-gfx at lists.freedesktop.org> <amd-gfx at lists.freedesktop.org<mailto:amd-gfx at lists.freedesktop.org>>
Cc: Chander, Vignesh <Vignesh.Chander at amd.com<mailto:Vignesh.Chander at amd.com>>; Lu, Victor Cheng Chi (Victor) <VictorChengChi.Lu at amd.com<mailto:VictorChengChi.Lu at amd.com>>
Subject: [PATCH 3/4] drm/amdgpu: Use correct SRIOV macro for gmc_v9_0_vm_fault_interrupt_state

Under SRIOV, programming to VM_CONTEXT*_CNTL regs failed because the
current macro does not pass through the correct xcc instance.
Use the *REG32_XCC macro in this case.

The behaviour without SRIOV is the same.

Signed-off-by: Victor Lu <victorchengchi.lu at amd.com<mailto:victorchengchi.lu at amd.com>>
---
 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index 473a774294ce..e2e14d40109c 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -496,14 +496,14 @@ static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
                                 if (j >= AMDGPU_MMHUB0(0))
                                         tmp = RREG32_SOC15_IP(MMHUB, reg);
                                 else
-                                       tmp = RREG32_SOC15_IP(GC, reg);
+                                       tmp = RREG32_XCC(reg, j);

                                 tmp &= ~bits;

                                 if (j >= AMDGPU_MMHUB0(0))
                                         WREG32_SOC15_IP(MMHUB, reg, tmp);
                                 else
-                                       WREG32_SOC15_IP(GC, reg, tmp);
+                                       WREG32_XCC(reg, tmp, j);
                         }
                 }
                 break;
@@ -524,14 +524,14 @@ static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
                                 if (j >= AMDGPU_MMHUB0(0))
                                         tmp = RREG32_SOC15_IP(MMHUB, reg);
                                 else
-                                       tmp = RREG32_SOC15_IP(GC, reg);
+                                       tmp = RREG32_XCC(reg, j);

                                 tmp |= bits;

                                 if (j >= AMDGPU_MMHUB0(0))
                                         WREG32_SOC15_IP(MMHUB, reg, tmp);
                                 else
-                                       WREG32_SOC15_IP(GC, reg, tmp);
+                                       WREG32_XCC(reg, tmp, j);
                         }
                 }
                 break;
--
2.34.1
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