[PATCH] drm/amdgpu/mes: use correct MES pipe for resets

[Chen, Michael]

[AMD Official Use Only - AMD Internal Distribution Only]

Reviewed-by: Michael Chen <michael.chen at amd.com>
________________________________
From: Deucher, Alexander <Alexander.Deucher at amd.com>
Sent: Tuesday, April 29, 2025 3:30 PM
To: amd-gfx at lists.freedesktop.org <amd-gfx at lists.freedesktop.org>
Cc: Deucher, Alexander <Alexander.Deucher at amd.com>; Chen, Michael <Michael.Chen at amd.com>; Liu, Shaoyun <Shaoyun.Liu at amd.com>
Subject: [PATCH] drm/amdgpu/mes: use correct MES pipe for resets

Use the KIQ pipe for kernel queues and the SCHED pipe for
user queues.

Fixes: a82b069d9eae ("drm/amdgpu/mes: consolidate on a single mes reset callback")
Cc: Michael Chen <Michael.Chen at amd.com>
Cc: Shaoyun Liu <Shaoyun.Liu at amd.com>
Signed-off-by: Alex Deucher <alexander.deucher at amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c | 1 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h | 1 +
 drivers/gpu/drm/amd/amdgpu/mes_v12_0.c  | 2 +-
 3 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
index 5de0d6c528f4e..2febb63ab2322 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
@@ -349,6 +349,7 @@ int amdgpu_mes_reset_legacy_queue(struct amdgpu_device *adev,
         queue_input.wptr_addr = ring->wptr_gpu_addr;
         queue_input.vmid = vmid;
         queue_input.use_mmio = use_mmio;
+       queue_input.is_kq = true;
         if (ring->funcs->type == AMDGPU_RING_TYPE_GFX)
                 queue_input.legacy_gfx = true;

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
index e98b0d892a593..a41f65b4f733a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
@@ -277,6 +277,7 @@ struct mes_reset_queue_input {
         uint64_t                           wptr_addr;
         uint32_t                           vmid;
         bool                               legacy_gfx;
+       bool                               is_kq;
 };

 enum mes_misc_opcode {
diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c b/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c
index f9f2fbc0a7166..b4f17332d4664 100644
--- a/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c
@@ -869,7 +869,7 @@ static int mes_v12_0_reset_hw_queue(struct amdgpu_mes *mes,
                 mes_reset_queue_pkt.doorbell_offset = input->doorbell_offset;
         }

-       if (mes->adev->enable_uni_mes)
+       if (input->is_kq)
                 pipe = AMDGPU_MES_KIQ_PIPE;
         else
                 pipe = AMDGPU_MES_SCHED_PIPE;
--
2.49.0

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