[PATCH 3/5] Documentation/gpu: Expand generic block information

Rodrigo Siqueira siqueira at igalia.com
Sat Aug 16 15:31:40 UTC 2025


This commit expands the overall explanation about AMD GPU IPs by adding
more details about their interconnection. Note that this commit includes
a diagram that provides additional information.

Cc: Alex Deucher <alexander.deucher at amd.com>
Cc: Christian König <christian.koenig at amd.com>
Cc: Timur Kristóf <timur.kristof at gmail.com>
Signed-off-by: Rodrigo Siqueira <siqueira at igalia.com>
---
 .../gpu/amdgpu/amd_overview_block.svg         | 674 ++++++++++++++++++
 Documentation/gpu/amdgpu/amdgpu-glossary.rst  |   3 +
 Documentation/gpu/amdgpu/driver-core.rst      |  25 +
 3 files changed, 702 insertions(+)
 create mode 100644 Documentation/gpu/amdgpu/amd_overview_block.svg

diff --git a/Documentation/gpu/amdgpu/amd_overview_block.svg b/Documentation/gpu/amdgpu/amd_overview_block.svg
new file mode 100644
index 000000000000..8d9ae95bd9a5
--- /dev/null
+++ b/Documentation/gpu/amdgpu/amd_overview_block.svg
@@ -0,0 +1,674 @@
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+           id="tspan23">Reset</tspan></text>
+    </g>
+    <path
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+         id="tspan26">PSP Interaction</tspan></text>
+    <path
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+         id="tspan34">UMC</tspan></text>
+    <text
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+         id="tspan35">UMC</tspan></text>
+    <path
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+           id="tspan40">Firmware</tspan></text>
+    </g>
+    <path
+       style="fill:none;stroke:#ffd42a;stroke-width:1;stroke-dasharray:8, 1;stroke-dashoffset:0"
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+    <path
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+         id="tspan42">Memory</tspan></text>
+    <text
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+         id="tspan43">Memory</tspan></text>
+    <text
+       xml:space="preserve"
+       style="font-style:normal;font-weight:normal;font-size:6.35px;line-height:1.25;font-family:sans-serif;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;stroke-width:0.0690111"
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+         id="tspan44">Memory</tspan></text>
+    <text
+       xml:space="preserve"
+       style="font-style:normal;font-weight:normal;font-size:6.35px;line-height:1.25;font-family:sans-serif;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;stroke-width:0.0690111"
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+         id="tspan45">Memory</tspan></text>
+    <path
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+    <path
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diff --git a/Documentation/gpu/amdgpu/amdgpu-glossary.rst b/Documentation/gpu/amdgpu/amdgpu-glossary.rst
index eb72e6f6d4f1..a3f9565d655b 100644
--- a/Documentation/gpu/amdgpu/amdgpu-glossary.rst
+++ b/Documentation/gpu/amdgpu/amdgpu-glossary.rst
@@ -227,6 +227,9 @@ we have a dedicated glossary for Display Core at
     TOC
       Table of Contents
 
+    UMC
+      Unified Memory Controller
+
     UMSCH
       User Mode Scheduler
 
diff --git a/Documentation/gpu/amdgpu/driver-core.rst b/Documentation/gpu/amdgpu/driver-core.rst
index 81256318e93c..f47199c04d8f 100644
--- a/Documentation/gpu/amdgpu/driver-core.rst
+++ b/Documentation/gpu/amdgpu/driver-core.rst
@@ -77,6 +77,31 @@ VCN (Video Core Next)
     decode.  It's exposed to userspace for user mode drivers (VA-API,
     OpenMAX, etc.)
 
+It is important to note that these blocks can interact with each other. The
+picture below illustrates some of the components and their interconnection:
+
+.. kernel-figure:: amd_overview_block.svg
+
+In the diagram, memory-related blocks are represented by a green color. Notice
+that specific IPs have a green block that represents a small hardware block
+named 'hub', which is responsible for interfacing with memory (pre-vega devices
+have a dedicated block for that, named GMC). In the driver code, you can
+identify this component by looking for the suffix hub, for example: gfxhub,
+dchub, mmhub, vmhub, etc. All memory hubs are connected in the UMC, which in
+turn is connected to memory blocks.
+
+There is some level of protection for certain elements in memory, and the PSP
+plays an essential role in this area. For example, when a specific firmware is
+loaded into the memory, PSP takes an action to ensure that the firmware has a
+valid signature. Another use of PSP is to support the TA (e.g., HDCP) and
+encrypted memory via TMZ.
+
+Another IP that deserves attention is the SMU, as it is connected to all the
+other IPs. SMU will help put the GPU in optimal utilization by taking into
+account performance and power consumption. SMU helps other blocks to set up a
+proper clock configuration. Another feature of SMU is the support for resetting
+every component.
+
 .. _pipes-and-queues-description:
 
 GFX, Compute, and SDMA Overall Behavior
-- 
2.47.2



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