[PATCH 5/5] Documentation/gpu: Add documentation about ring buffer
Rodrigo Siqueira
siqueira at igalia.com
Sat Aug 16 15:31:42 UTC 2025
AMDGPU heavily relies on ring buffers to manage its components; as a
result, it has an elaborate mechanism of operation with multiple details
around it. This commit introduces new documentation on ring buffers,
detailing their management and expanding the explanation of Enforce
isolation. Finally, this commit also adds the documentation available in
the amdgpu_ring.c file to it.
Cc: Alex Deucher <alexander.deucher at amd.com>
Cc: Christian König <christian.koenig at amd.com>
Cc: Timur Kristóf <timur.kristof at gmail.com>
Signed-off-by: Rodrigo Siqueira <siqueira at igalia.com>
---
.../gpu/amdgpu/enforce_isolation.svg | 707 +++++++
Documentation/gpu/amdgpu/gfx_pipeline_seq.svg | 413 +++++
Documentation/gpu/amdgpu/index.rst | 1 +
.../gpu/amdgpu/no_enforce_isolation.svg | 673 +++++++
Documentation/gpu/amdgpu/ring-buffer.rst | 94 +
Documentation/gpu/amdgpu/ring_buffers.svg | 1633 +++++++++++++++++
6 files changed, 3521 insertions(+)
create mode 100644 Documentation/gpu/amdgpu/enforce_isolation.svg
create mode 100644 Documentation/gpu/amdgpu/gfx_pipeline_seq.svg
create mode 100644 Documentation/gpu/amdgpu/no_enforce_isolation.svg
create mode 100644 Documentation/gpu/amdgpu/ring-buffer.rst
create mode 100644 Documentation/gpu/amdgpu/ring_buffers.svg
diff --git a/Documentation/gpu/amdgpu/enforce_isolation.svg b/Documentation/gpu/amdgpu/enforce_isolation.svg
new file mode 100644
index 000000000000..b224615e1611
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diff --git a/Documentation/gpu/amdgpu/index.rst b/Documentation/gpu/amdgpu/index.rst
index bb2894b5edaf..1f0e8a38c625 100644
--- a/Documentation/gpu/amdgpu/index.rst
+++ b/Documentation/gpu/amdgpu/index.rst
@@ -8,6 +8,7 @@ Next (GCN), Radeon DNA (RDNA), and Compute DNA (CDNA) architectures.
.. toctree::
driver-core
+ ring-buffer
amd-hardware-list-info
module-parameters
gc/index
diff --git a/Documentation/gpu/amdgpu/no_enforce_isolation.svg b/Documentation/gpu/amdgpu/no_enforce_isolation.svg
new file mode 100644
index 000000000000..38735447b005
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diff --git a/Documentation/gpu/amdgpu/ring-buffer.rst b/Documentation/gpu/amdgpu/ring-buffer.rst
new file mode 100644
index 000000000000..40c189c9dab4
--- /dev/null
+++ b/Documentation/gpu/amdgpu/ring-buffer.rst
@@ -0,0 +1,94 @@
+=============
+ Ring Buffer
+=============
+
+To handle communication between user space and kernel space, amdgpu adopts a
+strategy based on a ring buffer, which is used by GFX, Compute, SDMA, UVD, VCE,
+VCN, VPE, KIQ, MES, UMSCH, and CPER. See the figure below that illustrates how
+this communication works:
+
+.. kernel-figure:: ring_buffers.svg
+
+Ring buffers in the amdgpu work as a producer-consumer problem, where userspace
+acts as the producer, constantly filling the ring buffer with GPU commands to
+be executed. Meanwhile, the GPU retrieves the information from the ring, parses
+it, and distributes the specific set of instructions between the different
+amdgpu blocks. Notice from the diagram that the ring has a Read Pointer (rptr)
+that indicates where the GPU is currently reading, and there is a Write Pointer
+(wptr) that indicates where the host has written the message. Note that every
+time something is written to the ring, the wptr is incremented. Meanwhile, the
+GPU constantly updates the rptr pointer, chasing the wptr until both pointers
+are equal. The user space or the driver can utilize the rptr pointer to roughly
+estimate how many instructions are still pending completion (keep in mind that
+rptr might not be precise).
+
+Usually, ring buffers in the driver have a limited size (search for occurrences
+of `amdgpu_ring_init()`). One of the reasons for the small ring buffer size is
+that CP (Command Processor) is capable of following addresses inserted into the
+ring; this is illustrated in the image by the reference to the IB (Indirect
+Buffer). The IB gives userspace the possibility to have an area in memory that
+CP can read and feed the hardware with extra instructions.
+
+Enforce Isolation
+=================
+
+Before examining the Enforce Isolation mechanism in the ring buffer context, it
+is important to discuss two concepts: where the ring buffer is located and how
+instructions from the ring buffer are processed in the graphics pipeline.
+
+All ASICs pre-GFX11 use what is called a kernel queue, which means the ring is
+allocated in kernel space and has some restrictions, such as not being able to
+map and unmap queues after initialization. GFX12 and newer support kernel
+queues, but also provide a new mechanism named user queues, where the queue is
+moved to the user space and can be mapped and unmapped. In practical terms, the
+kernel queue approach inserts all GPU commands created by userspace into the
+same set of rings, albeit in a mixed manner. See the picture below illustrating
+this scenario:
+
+.. kernel-figure:: no_enforce_isolation.svg
+
+Note from the diagram that there is no guarantee of order or a clear separation
+between instructions, which is not a problem most of the time, and this is also
+good for performance. In terms of executing those instructions in the GFX, it
+must follow a pipeline that usually follows the following sequence: Shader
+Export (SX), Geometry Engine (GE), Shader Process or Input (SPI), Scan
+Converter (SC), Primitive Assembler (PA), and cache manipulation (this may
+change between ASICs). Another common way to describe the pipeline is to use
+Pixel Shader (PS), raster, and Vertex Shader (VS) to symbolize the two shader
+stages. The diagram below illustrates the sequence described in the paragraph.
+
+.. kernel-figure:: gfx_pipeline_seq.svg
+
+The use of the kernel queue is the default behaviour in amdgpu pre-GFX11 and in
+many cases in newer ASICs. Although this solution is considered stable and
+performs well, it also creates some intricate issues when something goes wrong.
+The problem with this solution is that pinpointing which job caused an issue
+can be challenging in some situations, which can complicate the debugging in
+circumstances where the GPU recovery was triggered. For instance, if Job A
+causes a hang issue, Job B's instruction might already be executing, and we
+could incorrectly identify Job B as the problematic one. To mitigate this
+problem, it was introduced the concept of Enforce Isolation that can be seen in
+the below picture:
+
+.. kernel-figure:: enforce_isolation.svg
+
+As shown in the diagram, enforcing isolation introduces a level of ordering
+between submissions, since the access to GFX/Compute is serialized. Notice that
+this approach has a minimal performance impact, as it only allows one job to
+submit commands at a time. However, this is not a notable problem, and the
+benefit of better pinpointing the job that caused a problem outweighs the
+performance impact. Although enforcing isolation improves the situation, it
+does not fully resolve the issue of pinpointing bad jobs, as we can still
+encounter scenarios where Job A hangs while Job B is running, leading to the
+wrong blame of Job B. To avoid this issue, an additional element is introduced
+to enforce isolation, as represented by the circles in the diagram. Every
+circle is a wait for cache flushing, which ensures that when the next job
+starts, it starts in a clean state, and if some issues happen, we can point to
+the bad process more precisely.
+
+Ring Operations
+===============
+
+.. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c
+ :internal:
+
diff --git a/Documentation/gpu/amdgpu/ring_buffers.svg b/Documentation/gpu/amdgpu/ring_buffers.svg
new file mode 100644
index 000000000000..7a6fcb19e151
--- /dev/null
+++ b/Documentation/gpu/amdgpu/ring_buffers.svg
@@ -0,0 +1,1633 @@
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+ id="tspan159">CP is capable of</tspan><tspan
+ sodipodi:role="line"
+ x="-68.488571"
+ y="260.07941"
+ style="font-style:normal;font-variant:normal;font-weight:bold;font-stretch:normal;font-size:7.76111px;font-family:sans-serif;-inkscape-font-specification:'sans-serif Bold';text-align:center;text-anchor:middle;fill:#1c241c;stroke-width:0.400612"
+ id="tspan160">following the</tspan><tspan
+ sodipodi:role="line"
+ x="-68.488571"
+ y="269.78079"
+ style="font-style:normal;font-variant:normal;font-weight:bold;font-stretch:normal;font-size:7.76111px;font-family:sans-serif;-inkscape-font-specification:'sans-serif Bold';text-align:center;text-anchor:middle;fill:#1c241c;stroke-width:0.400612"
+ id="tspan161">IB address.</tspan></text>
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+</svg>
--
2.47.2
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