[PATCH] drm/amd/include : Update MES v12 API for fence update

[Alex Deucher]

On Wed, Feb 5, 2025 at 1:52 PM Shaoyun Liu <shaoyun.liu at amd.com> wrote:
>
> MES fence_value will be updated in fence_addr if API success,
> otherwise upper 32 bit will be used to indicate error code.
> In any case, MES will trigger an EOP interrupt with 0xb1 as
> context id in the interrupt cookie
>
> Signed-off-by: Shaoyun Liu <shaoyun.liu at amd.com>

Acked-by: Alex Deucher <alexander.deucher at amd.com>

> ---
>  drivers/gpu/drm/amd/include/mes_v12_api_def.h | 40 ++++++++++++++++++-
>  1 file changed, 39 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/include/mes_v12_api_def.h b/drivers/gpu/drm/amd/include/mes_v12_api_def.h
> index 1938150a1943..fb918668ddae 100644
> --- a/drivers/gpu/drm/amd/include/mes_v12_api_def.h
> +++ b/drivers/gpu/drm/amd/include/mes_v12_api_def.h
> @@ -105,6 +105,43 @@ struct MES_API_STATUS {
>         uint64_t api_completion_fence_value;
>  };
>
> +/*
> + * MES will set api_completion_fence_value in api_completion_fence_addr
> + * when it can successflly process the API. MES will also trigger
> + * following interrupt when it finish process the API no matter success
> + * or failed.
> + *     Interrupt source id 181 (EOP) with context ID (DW 6 in the int
> + *     cookie) set to 0xb1 and context type set to 8. Driver side need
> + *     to enable TIME_STAMP_INT_ENABLE in CPC_INT_CNTL for MES pipe to
> + *     catch this interrupt.
> + *     Driver side also need to set enable_mes_fence_int = 1 in
> + *     set_HW_resource package to enable this fence interrupt.
> + * when the API process failed.
> + *     lowre 32 bits set to 0.
> + *     higher 32 bits set as follows (bit shift within high 32)
> + *         bit 0  -  7    API specific error code.
> + *         bit 8  - 15    API OPCODE.
> + *         bit 16 - 23    MISC OPCODE if any
> + *         bit 24 - 30    ERROR category (API_ERROR_XXX)
> + *         bit 31         Set to 1 to indicate error status
> + *
> + */
> +enum { MES_SCH_ERROR_CODE_HEADER_SHIFT_12 = 8 };
> +enum { MES_SCH_ERROR_CODE_MISC_OP_SHIFT_12 = 16 };
> +enum { MES_ERROR_CATEGORY_SHIFT_12 = 24 };
> +enum { MES_API_STATUS_ERROR_SHIFT_12 = 31 };
> +
> +enum MES_ERROR_CATEGORY_CODE_12 {
> +       MES_ERROR_API                = 1,
> +       MES_ERROR_SCHEDULING         = 2,
> +       MES_ERROR_UNKNOWN            = 3,
> +};
> +
> +#define MES_ERR_CODE(api_err, opcode, misc_op, category) \
> +                       ((uint64) (api_err | opcode << MES_SCH_ERROR_CODE_HEADER_SHIFT_12 | \
> +                       misc_op << MES_SCH_ERROR_CODE_MISC_OP_SHIFT_12 | \
> +                       category << MES_ERROR_CATEGORY_SHIFT_12 | \
> +                       1 << MES_API_STATUS_ERROR_SHIFT_12) << 32)
>
>  enum { MAX_COMPUTE_PIPES = 8 };
>  enum { MAX_GFX_PIPES    = 2 };
> @@ -248,7 +285,8 @@ union MESAPI_SET_HW_RESOURCES {
>                                 uint32_t enable_mes_sch_stb_log : 1;
>                                 uint32_t limit_single_process : 1;
>                                 uint32_t unmapped_doorbell_handling: 2;
> -                               uint32_t reserved : 11;
> +                               uint32_t enable_mes_fence_int: 1;
> +                               uint32_t reserved : 10;
>                         };
>                         uint32_t uint32_all;
>                 };
> --
> 2.34.1
>