[PATCH 1/2] drm/amdgpu/gfx11: fix num_mec

Deucher, Alexander Alexander.Deucher at amd.com
Wed Mar 26 15:51:00 UTC 2025


[AMD Official Use Only - AMD Internal Distribution Only]

We could clean that up, but if we did so, we should add a second switch statement for the userq_funcs assignments so we can enable them selectively as the firmwares become available.

Alex

________________________________
From: Khatri, Sunil <Sunil.Khatri at amd.com>
Sent: Wednesday, March 26, 2025 11:36 AM
To: Deucher, Alexander <Alexander.Deucher at amd.com>; amd-gfx at lists.freedesktop.org <amd-gfx at lists.freedesktop.org>
Cc: Deucher, Alexander <Alexander.Deucher at amd.com>
Subject: RE: [PATCH 1/2] drm/amdgpu/gfx11: fix num_mec

[AMD Official Use Only - AMD Internal Distribution Only]

Gfx11 now we have same values, hence we don’t need to differentiate between two sets , only one set is needed like below.

As below
case IP_VERSION(11, 0, 0):
        case IP_VERSION(11, 0, 2):
        case IP_VERSION(11, 0, 3):
        case IP_VERSION(11, 0, 1):
        case IP_VERSION(11, 0, 4):
        case IP_VERSION(11, 5, 0):
        case IP_VERSION(11, 5, 1):
        case IP_VERSION(11, 5, 2):
        case IP_VERSION(11, 5, 3):
                adev->gfx.me.num_me = 1;
                adev->gfx.me.num_pipe_per_me = 1;
                adev->gfx.me.num_queue_per_pipe = 1;
                adev->gfx.mec.num_mec = 1;
                adev->gfx.mec.num_pipe_per_mec = 4;
                adev->gfx.mec.num_queue_per_pipe = 4;
#ifdef CONFIG_DRM_AMDGPU_NAVI3X_USERQ
                adev->userq_funcs[AMDGPU_HW_IP_GFX] = &userq_mes_funcs;
                adev->userq_funcs[AMDGPU_HW_IP_COMPUTE] = &userq_mes_funcs;
#endif
                        break;

Regards
Sunil Khatri

-----Original Message-----
From: amd-gfx <amd-gfx-bounces at lists.freedesktop.org> On Behalf Of Alex Deucher
Sent: Wednesday, March 26, 2025 7:13 PM
To: amd-gfx at lists.freedesktop.org
Cc: Deucher, Alexander <Alexander.Deucher at amd.com>
Subject: [PATCH 1/2] drm/amdgpu/gfx11: fix num_mec

GC11 only has 1 mec.

Fixes: 3d879e81f0f9 ("drm/amdgpu: add init support for GFX11 (v2)")
Signed-off-by: Alex Deucher <alexander.deucher at amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
index e0a9b10d645c6..a9ef33205c541 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
@@ -1573,7 +1573,7 @@ static int gfx_v11_0_sw_init(struct amdgpu_ip_block *ip_block)
                adev->gfx.me.num_me = 1;
                adev->gfx.me.num_pipe_per_me = 1;
                adev->gfx.me.num_queue_per_pipe = 1;
-               adev->gfx.mec.num_mec = 2;
+               adev->gfx.mec.num_mec = 1;
                adev->gfx.mec.num_pipe_per_mec = 4;
                adev->gfx.mec.num_queue_per_pipe = 4;  #ifdef CONFIG_DRM_AMDGPU_NAVI3X_USERQ
--
2.49.0

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