[PATCH 4/4] drm/amd/display: Replace dcn35_update_odm with dcn314_update_odm

[Rodrigo Siqueira]

dcn35_update_odm has the same implementation as dcn314_update_odm. This
commit removes the duplicate implementation by using dcn314_update_odm
in the DCN35 code.

Signed-off-by: Rodrigo Siqueira <siqueira at igalia.com>
---
 .../amd/display/dc/hwss/dcn35/dcn35_hwseq.c   | 52 -------------------
 .../amd/display/dc/hwss/dcn35/dcn35_hwseq.h   |  2 -
 .../amd/display/dc/hwss/dcn35/dcn35_init.c    |  2 +-
 .../amd/display/dc/hwss/dcn351/dcn351_init.c  |  3 +-
 4 files changed, 3 insertions(+), 56 deletions(-)

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
index 922b8d71cf1a..abcbd1759465 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
@@ -420,58 +420,6 @@ static unsigned int get_odm_config(struct pipe_ctx *pipe_ctx, unsigned int *opp_
 	return opp_count;
 }
 
-void dcn35_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx)
-{
-	struct pipe_ctx *odm_pipe;
-	int opp_cnt = 0;
-	int opp_inst[MAX_PIPES] = {0};
-	int odm_slice_width = resource_get_odm_slice_dst_width(pipe_ctx, false);
-	int last_odm_slice_width = resource_get_odm_slice_dst_width(pipe_ctx, true);
-	struct mpc *mpc = dc->res_pool->mpc;
-	int i;
-
-	opp_cnt = get_odm_config(pipe_ctx, opp_inst);
-
-	if (opp_cnt > 1)
-		pipe_ctx->stream_res.tg->funcs->set_odm_combine(
-				pipe_ctx->stream_res.tg,
-				opp_inst, opp_cnt,
-				odm_slice_width, last_odm_slice_width);
-	else
-		pipe_ctx->stream_res.tg->funcs->set_odm_bypass(
-				pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);
-
-	if (mpc->funcs->set_out_rate_control) {
-		for (i = 0; i < opp_cnt; ++i) {
-			mpc->funcs->set_out_rate_control(
-					mpc, opp_inst[i],
-					false,
-					0,
-					NULL);
-		}
-	}
-
-	for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
-		odm_pipe->stream_res.opp->funcs->opp_pipe_clock_control(
-				odm_pipe->stream_res.opp,
-				true);
-	}
-
-	if (pipe_ctx->stream_res.dsc) {
-		struct pipe_ctx *current_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[pipe_ctx->pipe_idx];
-
-		update_dsc_on_stream(pipe_ctx, pipe_ctx->stream->timing.flags.DSC);
-
-		/* Check if no longer using pipe for ODM, then need to disconnect DSC for that pipe */
-		if (!pipe_ctx->next_odm_pipe && current_pipe_ctx->next_odm_pipe &&
-				current_pipe_ctx->next_odm_pipe->stream_res.dsc) {
-			struct display_stream_compressor *dsc = current_pipe_ctx->next_odm_pipe->stream_res.dsc;
-			/* disconnect DSC block from stream */
-			dsc->funcs->dsc_disconnect(dsc);
-		}
-	}
-}
-
 void dcn35_dpp_root_clock_control(struct dce_hwseq *hws, unsigned int dpp_inst, bool clock_on)
 {
 	if (!hws->ctx->dc->debug.root_clock_optimization.bits.dpp)
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h
index 0b1d6f608edd..6ca6924e7379 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.h
@@ -31,8 +31,6 @@
 
 struct dc;
 
-void dcn35_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx);
-
 void dcn35_dsc_pg_control(struct dce_hwseq *hws, unsigned int dsc_inst, bool power_on);
 
 void dcn35_dpp_root_clock_control(struct dce_hwseq *hws, unsigned int dpp_inst, bool clock_on);
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_init.c
index a3ccf805bd16..3a14c6374324 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_init.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_init.c
@@ -155,7 +155,7 @@ static const struct hwseq_private_funcs dcn35_private_funcs = {
 	.dpstream_root_clock_control = dcn35_dpstream_root_clock_control,
 	.physymclk_root_clock_control = dcn35_physymclk_root_clock_control,
 	.program_all_writeback_pipes_in_tree = dcn30_program_all_writeback_pipes_in_tree,
-	.update_odm = dcn35_update_odm,
+	.update_odm = dcn314_update_odm,
 	.set_hdr_multiplier = dcn10_set_hdr_multiplier,
 	.verify_allow_pstate_change_high = dcn10_verify_allow_pstate_change_high,
 	.wait_for_blank_complete = dcn20_wait_for_blank_complete,
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_init.c
index 58f2be2a326b..24bd1bbf4461 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_init.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_init.c
@@ -30,6 +30,7 @@
 #include "dcn30/dcn30_hwseq.h"
 #include "dcn301/dcn301_hwseq.h"
 #include "dcn31/dcn31_hwseq.h"
+#include "dcn314/dcn314_hwseq.h"
 #include "dcn32/dcn32_hwseq.h"
 #include "dcn35/dcn35_hwseq.h"
 #include "dcn351/dcn351_hwseq.h"
@@ -150,7 +151,7 @@ static const struct hwseq_private_funcs dcn351_private_funcs = {
 	.dpstream_root_clock_control = dcn35_dpstream_root_clock_control,
 	.physymclk_root_clock_control = dcn35_physymclk_root_clock_control,
 	.program_all_writeback_pipes_in_tree = dcn30_program_all_writeback_pipes_in_tree,
-	.update_odm = dcn35_update_odm,
+	.update_odm = dcn314_update_odm,
 	.set_hdr_multiplier = dcn10_set_hdr_multiplier,
 	.verify_allow_pstate_change_high = dcn10_verify_allow_pstate_change_high,
 	.wait_for_blank_complete = dcn20_wait_for_blank_complete,
-- 
2.47.2