[PATCH v4] drm/amdgpu: read back register after written for VCN v4.0.5

[Deucher, Alexander]

[Public]

Reviewed-by: Alex Deucher <alexander.deucher at amd.com>

________________________________
From: Wu, David <David.Wu3 at amd.com>
Sent: Tuesday, May 13, 2025 6:12 PM
To: amd-gfx at lists.freedesktop.org <amd-gfx at lists.freedesktop.org>; Koenig, Christian <Christian.Koenig at amd.com>
Cc: Deucher, Alexander <Alexander.Deucher at amd.com>; Liu, Leo <Leo.Liu at amd.com>; Jiang, Sonny <Sonny.Jiang at amd.com>; Dong, Ruijing <Ruijing.Dong at amd.com>; stable at vger.kernel.org <stable at vger.kernel.org>; Limonciello, Mario <Mario.Limonciello at amd.com>
Subject: [PATCH v4] drm/amdgpu: read back register after written for VCN v4.0.5

V4: add read-back for non-DPG case. This is for protection
    purpose as it is not used for producton.

On VCN v4.0.5 there is a race condition where the WPTR is not
updated after starting from idle when doorbell is used. Adding
register read-back after written at function end is to ensure
all register writes are done before they can be used.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/12528
Cc: stable at vger.kernel.org

Signed-off-by: David (Ming Qiang) Wu <David.Wu3 at amd.com>
Reviewed-by: Mario Limonciello <mario.limonciello at amd.com>
Tested-by: Mario Limonciello <mario.limonciello at amd.com>
---
 drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
index ed00d35039c1..a09f9a2dd471 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
@@ -1034,6 +1034,10 @@ static int vcn_v4_0_5_start_dpg_mode(struct amdgpu_vcn_inst *vinst,
                         ring->doorbell_index << VCN_RB1_DB_CTRL__OFFSET__SHIFT |
                         VCN_RB1_DB_CTRL__EN_MASK);

+       /* Keeping one read-back to ensure all register writes are done, otherwise
+        * it may introduce race conditions */
+       RREG32_SOC15(VCN, inst_idx, regVCN_RB1_DB_CTRL);
+
         return 0;
 }

@@ -1216,6 +1220,10 @@ static int vcn_v4_0_5_start(struct amdgpu_vcn_inst *vinst)
         WREG32_SOC15(VCN, i, regVCN_RB_ENABLE, tmp);
         fw_shared->sq.queue_mode &= ~(FW_QUEUE_RING_RESET | FW_QUEUE_DPG_HOLD_OFF);

+       /* Keeping one read-back to ensure all register writes are done, otherwise
+        * it may introduce race conditions */
+       RREG32_SOC15(VCN, i, regVCN_RB_ENABLE);
+
         return 0;
 }

--
2.34.1

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