[Beignet] [PATCH] CL/Driver: enable atomics in L3 for HSW.

[Zhenyu Wang]

On 2014.12.31 10:02:30 +0800, Zhigang Gong wrote:
> This could get more than 10x boost for some atomic stress workloads.
>

But this will be filtered by cmd parser.

From kernel log,

commit f3fc4884ebe6ae649d3723be14b219230d3b7fd2
Author: Francisco Jerez <currojerez at riseup.net>
Date:   Wed Oct 2 15:53:16 2013 -0700

    drm/i915/hsw: Disable L3 caching of atomic memory operations.
    
    Otherwise using any atomic memory operation will lock up the GPU due
    to a Haswell hardware bug.
    
Maybe this issue affects some HSW stepping, should just fix the kernel.

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Open Source Technology Center, Intel ltd.

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