[Beignet] [PATCH] CL/Driver: enable atomics in L3 for HSW.

[Gong, Zhigang]

> -----Original Message-----
> From: Zhenyu Wang [mailto:zhenyuw at linux.intel.com]
> Sent: Wednesday, December 31, 2014 11:10 AM
> To: Gong, Zhigang
> Cc: beignet at lists.freedesktop.org
> Subject: Re: [Beignet] [PATCH] CL/Driver: enable atomics in L3 for HSW.
> 
> On 2014.12.31 10:02:30 +0800, Zhigang Gong wrote:
> > This could get more than 10x boost for some atomic stress workloads.
> >
> 
> But this will be filtered by cmd parser.

Right. It could only take effect if we applied the work around patch.
For anyone who want to use beignet on HSW, the kernel work around
patch is a must currently.

> 
> From kernel log,
> 
> commit f3fc4884ebe6ae649d3723be14b219230d3b7fd2
> Author: Francisco Jerez <currojerez at riseup.net>
> Date:   Wed Oct 2 15:53:16 2013 -0700
> 
>     drm/i915/hsw: Disable L3 caching of atomic memory operations.
> 
>     Otherwise using any atomic memory operation will lock up the GPU due
>     to a Haswell hardware bug.
> 
> Maybe this issue affects some HSW stepping, should just fix the kernel.

That should be a hardware bug for the version earlier than stepping D.
And I think this should not be a real problem now, as all HSW we can get
from public channel is at least stepping D or newer. I will submit a kernel
patch latter. Before that patch has been accepted by kernel, I would rather
to push this patch to beignet. As some application will affected heavily by
this issue, such as the darktable's splat kernel. The splat kernel uses many
atomic operations, and may take 50 seconds on one image, but with this patch
it just takes less than 1 second.

Any thoughts?


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