[Beignet] [PATCH] GBE: fix one regression caused by uniform analysis.

[Zhigang Gong]

Some instructions handle simd1 incorrectly. Disable them
currently.

Signed-off-by: Zhigang Gong <zhigang.gong at intel.com>
---
 backend/src/ir/liveness.cpp | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/backend/src/ir/liveness.cpp b/backend/src/ir/liveness.cpp
index e36b194..6b02296 100644
--- a/backend/src/ir/liveness.cpp
+++ b/backend/src/ir/liveness.cpp
@@ -76,11 +76,15 @@ namespace ir {
     // A destination is a killed value
     for (uint32_t dstID = 0; dstID < dstNum; ++dstID) {
       const Register reg = insn.getDst(dstID);
+      int opCode = insn.getOpcode();
       if ( uniform &&
           fn.getRegisterFamily(reg) != ir::FAMILY_BOOL &&
           fn.getRegisterFamily(reg) != ir::FAMILY_QWORD &&
           !info.bb.definedPhiRegs.contains(reg) &&
-          insn.getOpcode() != ir::OP_ATOMIC &&
+          opCode != ir::OP_ATOMIC &&
+          opCode != ir::OP_MUL_HI &&
+          opCode != ir::OP_HADD &&
+          opCode != ir::OP_RHADD &&
           (dstNum == 1 || insn.getOpcode() != ir::OP_LOAD)
          )
         fn.setRegisterUniform(reg, true);
-- 
1.8.3.2