[Beignet] [PATCH] GBE: fix one regression caused by uniform analysis.

Zhigang Gong zhigang.gong at linux.intel.com
Tue May 13 04:26:16 PDT 2014


Forgot to rebase to master, please ignore this one. A new version has been
sent.

> -----Original Message-----
> From: Beignet [mailto:beignet-bounces at lists.freedesktop.org] On Behalf Of
> Zhigang Gong
> Sent: Tuesday, May 13, 2014 6:33 PM
> To: beignet at lists.freedesktop.org
> Cc: Zhigang Gong
> Subject: [Beignet] [PATCH] GBE: fix one regression caused by uniform
analysis.
> 
> Some instructions handle simd1 incorrectly. Disable them currently.
> 
> Signed-off-by: Zhigang Gong <zhigang.gong at intel.com>
> ---
>  backend/src/ir/liveness.cpp | 6 +++++-
>  1 file changed, 5 insertions(+), 1 deletion(-)
> 
> diff --git a/backend/src/ir/liveness.cpp b/backend/src/ir/liveness.cpp
index
> e36b194..6b02296 100644
> --- a/backend/src/ir/liveness.cpp
> +++ b/backend/src/ir/liveness.cpp
> @@ -76,11 +76,15 @@ namespace ir {
>      // A destination is a killed value
>      for (uint32_t dstID = 0; dstID < dstNum; ++dstID) {
>        const Register reg = insn.getDst(dstID);
> +      int opCode = insn.getOpcode();
>        if ( uniform &&
>            fn.getRegisterFamily(reg) != ir::FAMILY_BOOL &&
>            fn.getRegisterFamily(reg) != ir::FAMILY_QWORD &&
>            !info.bb.definedPhiRegs.contains(reg) &&
> -          insn.getOpcode() != ir::OP_ATOMIC &&
> +          opCode != ir::OP_ATOMIC &&
> +          opCode != ir::OP_MUL_HI &&
> +          opCode != ir::OP_HADD &&
> +          opCode != ir::OP_RHADD &&
>            (dstNum == 1 || insn.getOpcode() != ir::OP_LOAD)
>           )
>          fn.setRegisterUniform(reg, true);
> --
> 1.8.3.2
> 
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