[Beignet] [PATCH] correct L3 cache settings for baytrail

[Guo Yejun]

baytrail and ivb have different register bits layout for L3 cache,
so, add a special path for baytrail.

Signed-off-by: Guo Yejun <yejun.guo at intel.com>
---
 src/intel/intel_gpgpu.c | 37 ++++++++++++++++++++++++++++++++++---
 1 file changed, 34 insertions(+), 3 deletions(-)

diff --git a/src/intel/intel_gpgpu.c b/src/intel/intel_gpgpu.c
index b7b712f..59d9a7a 100644
--- a/src/intel/intel_gpgpu.c
+++ b/src/intel/intel_gpgpu.c
@@ -309,14 +309,14 @@ static const uint32_t gpgpu_l3_config_reg1[] = {
   0x00080040, 0x02040040, 0x00800040, 0x01000038,
   0x02000030, 0x01000038, 0x00000038, 0x00000040,
   0x0A140091, 0x09100091, 0x08900091, 0x08900091,
-  0x010000a1
+  0x010000a1, 0x02040001, 0x02040040
 };
 
 static const uint32_t gpgpu_l3_config_reg2[] = {
   0x00000000, 0x00000000, 0x00080410, 0x00080410,
   0x00040410, 0x00040420, 0x00080420, 0x00080020,
   0x00204080, 0x00244890, 0x00284490, 0x002444A0,
-  0x00040810
+  0x00040810, 0x00000000, 0x00000000
 };
 
 /* Emit PIPE_CONTROLs to write the current GPU timestamp into a buffer. */
@@ -383,6 +383,34 @@ intel_gpgpu_set_L3_gen7(intel_gpgpu_t *gpgpu, uint32_t use_slm)
 }
 
 static void
+intel_gpgpu_set_L3_baytrail(intel_gpgpu_t *gpgpu, uint32_t use_slm)
+{
+  BEGIN_BATCH(gpgpu->batch, 9);
+
+  OUT_BATCH(gpgpu->batch, CMD_LOAD_REGISTER_IMM | 1); /* length - 2 */
+  OUT_BATCH(gpgpu->batch, GEN7_L3_SQC_REG1_ADDRESS_OFFSET);
+  OUT_BATCH(gpgpu->batch, 0x00D30000);
+
+  OUT_BATCH(gpgpu->batch, CMD_LOAD_REGISTER_IMM | 1); /* length - 2 */
+  OUT_BATCH(gpgpu->batch, GEN7_L3_CNTL_REG2_ADDRESS_OFFSET);
+  if (use_slm)
+    OUT_BATCH(gpgpu->batch, gpgpu_l3_config_reg1[13]);
+  else
+    OUT_BATCH(gpgpu->batch, gpgpu_l3_config_reg1[14]);
+
+  OUT_BATCH(gpgpu->batch, CMD_LOAD_REGISTER_IMM | 1); /* length - 2 */
+  OUT_BATCH(gpgpu->batch, GEN7_L3_CNTL_REG3_ADDRESS_OFFSET);
+  if (use_slm)
+    OUT_BATCH(gpgpu->batch, gpgpu_l3_config_reg2[13]);
+  else
+    OUT_BATCH(gpgpu->batch, gpgpu_l3_config_reg2[14]);
+
+  ADVANCE_BATCH(gpgpu->batch);
+
+  intel_gpgpu_pipe_control(gpgpu);
+}
+
+static void
 intel_gpgpu_set_L3_gen75(intel_gpgpu_t *gpgpu, uint32_t use_slm)
 {
   /* still set L3 in batch buffer for fulsim. */
@@ -1179,7 +1207,10 @@ intel_set_gpgpu_callbacks(int device_id)
   }
   else if (IS_IVYBRIDGE(device_id)) {
     cl_gpgpu_bind_image = (cl_gpgpu_bind_image_cb *) intel_gpgpu_bind_image_gen7;
-    intel_gpgpu_set_L3 = intel_gpgpu_set_L3_gen7;
+    if (IS_BAYTRAIL_T(device_id))
+      intel_gpgpu_set_L3 = intel_gpgpu_set_L3_baytrail;
+    else
+      intel_gpgpu_set_L3 = intel_gpgpu_set_L3_gen7;
     get_scratch_index = get_scratch_index_gen7;
   }
   else
-- 
1.8.3.2