[Beignet] [PATCH] correct L3 cache settings for baytrail
Song, Ruiling
ruiling.song at intel.com
Thu May 22 01:26:48 PDT 2014
--- a/src/intel/intel_gpgpu.c
+++ b/src/intel/intel_gpgpu.c
@@ -309,14 +309,14 @@ static const uint32_t gpgpu_l3_config_reg1[] = {
0x00080040, 0x02040040, 0x00800040, 0x01000038,
0x02000030, 0x01000038, 0x00000038, 0x00000040,
0x0A140091, 0x09100091, 0x08900091, 0x08900091,
- 0x010000a1
+ 0x010000a1, 0x02040001, 0x02040040
};
static const uint32_t gpgpu_l3_config_reg2[] = {
0x00000000, 0x00000000, 0x00080410, 0x00080410,
0x00040410, 0x00040420, 0x00080420, 0x00080020,
0x00204080, 0x00244890, 0x00284490, 0x002444A0,
- 0x00040810
+ 0x00040810, 0x00000000, 0x00000000
};
I would suggest you use another array, don't mixed the configuration, as different HW cannot share the configuration table.
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