[Beignet] [PATCH] correct the cache line size to be 64

[Guo Yejun]

the correct value of cache line size is 64 bytes, not 128.

Signed-off-by: Guo Yejun <yejun.guo at intel.com>
---
 src/cl_gen75_device.h | 2 +-
 src/cl_gen7_device.h  | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/cl_gen75_device.h b/src/cl_gen75_device.h
index 8cf2dcd..43f6e8f 100644
--- a/src/cl_gen75_device.h
+++ b/src/cl_gen75_device.h
@@ -20,7 +20,7 @@
 /* Common fields for both SNB devices (either GT1 or GT2)
  */
 .max_parameter_size = 1024,
-.global_mem_cache_line_size = 128, /* XXX */
+.global_mem_cache_line_size = 64, /* XXX */
 .global_mem_cache_size = 8 << 10, /* XXX */
 .local_mem_type = CL_GLOBAL,
 .local_mem_size = 64 << 10,
diff --git a/src/cl_gen7_device.h b/src/cl_gen7_device.h
index 6857f8a..4ad5d96 100644
--- a/src/cl_gen7_device.h
+++ b/src/cl_gen7_device.h
@@ -19,7 +19,7 @@
 
 /* Common fields for both IVB devices (either GT1 or GT2) */
 .max_parameter_size = 1024,
-.global_mem_cache_line_size = 128, /* XXX */
+.global_mem_cache_line_size = 64, /* XXX */
 .global_mem_cache_size = 8 << 10, /* XXX */
 .local_mem_type = CL_GLOBAL,
 .local_mem_size = 64 << 10,
-- 
1.9.1