[Beignet] [PATCH] add atomic operators output for GEN_IR and gen disa.

[Yang, Rong R]

LGTM, thanks.

> -----Original Message-----
> From: Beignet [mailto:beignet-bounces at lists.freedesktop.org] On Behalf Of
> xionghu.luo at intel.com
> Sent: Tuesday, April 21, 2015 09:46
> To: beignet at lists.freedesktop.org
> Cc: Luo, Xionghu
> Subject: [Beignet] [PATCH] add atomic operators output for GEN_IR and gen
> disa.
> 
> From: Luo Xionghu <xionghu.luo at intel.com>
> 
> the function types of atomic instruction are useful for analyzing the gen ir
> and disassembly.
> 
> Signed-off-by: Luo Xionghu <xionghu.luo at intel.com>
> ---
>  backend/src/backend/gen/gen_mesa_disasm.c | 40
> ++++++++++++++++++++++++++-----
>  backend/src/ir/instruction.cpp            | 27 ++++++++++++++++++++-
>  2 files changed, 60 insertions(+), 7 deletions(-)
> 
> diff --git a/backend/src/backend/gen/gen_mesa_disasm.c
> b/backend/src/backend/gen/gen_mesa_disasm.c
> index 711b943..0b5591f 100644
> --- a/backend/src/backend/gen/gen_mesa_disasm.c
> +++ b/backend/src/backend/gen/gen_mesa_disasm.c
> @@ -449,6 +449,24 @@ static const char
> *data_port1_data_cache_msg_type[] = {
>    [13] = "Typed Surface Write",
>  };
> 
> +static const char *atomic_opration_type[] = {
> +  [1] = "and",
> +  [2] = "or",
> +  [3] = "xor",
> +  [4] = "xchg",
> +  [5] = "inc",
> +  [6] = "dec",
> +  [7] = "add",
> +  [8] = "sub",
> +  [9] = "rsub",
> +  [10] = "imax",
> +  [11] = "imin",
> +  [12] = "umax",
> +  [13] = "umin",
> +  [14] = "cmpxchg",
> +  [15] = "invalid"
> +};
> +
>  static int column;
> 
>  static int gen_version;
> @@ -505,6 +523,7 @@ static int gen_version;  #define
> UNTYPED_RW_SIMD_MODE(inst) GEN_BITS_FIELD(inst,
> bits3.gen7_untyped_rw.simd_mode)  #define
> UNTYPED_RW_CATEGORY(inst)  GEN_BITS_FIELD(inst,
> bits3.gen7_untyped_rw.category)  #define UNTYPED_RW_MSG_TYPE(inst)
> GEN_BITS_FIELD(inst, bits3.gen7_untyped_rw.msg_type)
> +#define UNTYPED_RW_AOP_TYPE(inst)  GEN_BITS_FIELD(inst,
> +bits3.gen7_atomic_op.aop_type)
>  #define SCRATCH_RW_OFFSET(inst)    GEN_BITS_FIELD(inst,
> bits3.gen7_scratch_rw.offset)
>  #define SCRATCH_RW_BLOCK_SIZE(inst) GEN_BITS_FIELD(inst,
> bits3.gen7_scratch_rw.block_size)  #define
> SCRATCH_RW_INVALIDATE_AFTER_READ(inst) GEN_BITS_FIELD(inst,
> bits3.gen7_scratch_rw.invalidate_after_read)
> @@ -1259,12 +1278,21 @@ int gen_disasm (FILE *file, const void *inst,
> uint32_t deviceID, uint32_t compac
>          break;
>        case GEN_SFID_DATAPORT_DATA:
>          if(UNTYPED_RW_CATEGORY(inst) == 0) {
> -          format(file, " (bti: %d, rgba: %d, %s, %s, %s)",
> -                 UNTYPED_RW_BTI(inst),
> -                 UNTYPED_RW_RGBA(inst),
> -
> data_port_data_cache_simd_mode[UNTYPED_RW_SIMD_MODE(inst)],
> -                 data_port_data_cache_category[UNTYPED_RW_CATEGORY(inst)],
> -
> data_port_data_cache_msg_type[UNTYPED_RW_MSG_TYPE(inst)]);
> +          if(UNTYPED_RW_MSG_TYPE(inst) == 6)
> +            format(file, " (bti: %d, rgba: %d, %s, %s, %s, %s)",
> +                UNTYPED_RW_BTI(inst),
> +                UNTYPED_RW_RGBA(inst),
> +
> data_port_data_cache_simd_mode[UNTYPED_RW_SIMD_MODE(inst)],
> +                data_port_data_cache_category[UNTYPED_RW_CATEGORY(inst)],
> +                data_port_data_cache_msg_type[UNTYPED_RW_MSG_TYPE(inst)],
> +                atomic_opration_type[UNTYPED_RW_AOP_TYPE(inst)]);
> +          else
> +            format(file, " (bti: %d, rgba: %d, %s, %s, %s)",
> +                UNTYPED_RW_BTI(inst),
> +                UNTYPED_RW_RGBA(inst),
> +
> data_port_data_cache_simd_mode[UNTYPED_RW_SIMD_MODE(inst)],
> +                data_port_data_cache_category[UNTYPED_RW_CATEGORY(inst)],
> +
> + data_port_data_cache_msg_type[UNTYPED_RW_MSG_TYPE(inst)]);
>          } else {
>            format(file, " (addr: %d, blocks: %s, %s, mode: %s, %s)",
>                   SCRATCH_RW_OFFSET(inst), diff --git
> a/backend/src/ir/instruction.cpp b/backend/src/ir/instruction.cpp index
> 797552f..1bfb996 100644
> --- a/backend/src/ir/instruction.cpp
> +++ b/backend/src/ir/instruction.cpp
> @@ -340,7 +340,7 @@ namespace ir {
>        AddressSpace addrSpace; //!< Address space
>        BTI bti;               //!< bti
>        uint8_t srcNum:2;     //!<Source Number
> -      AtomicOps atomicOp:6;     //!<Source Number
> +      AtomicOps atomicOp:6;     //!<Source Operator
>      };
> 
>      class ALIGNED_INSTRUCTION BranchInstruction :
> @@ -1153,6 +1153,31 @@ namespace ir {
>      INLINE void AtomicInstruction::out(std::ostream &out, const Function &fn)
> const {
>        this->outOpcode(out);
>        out << "." << addrSpace;
> +
> +#define OUT_ATOMIC_OP(TYPE)     \
> +      case ATOMIC_OP_##TYPE:    \
> +      {    out << "." << #TYPE; \
> +          break; \
> +      }
> +      switch(atomicOp)
> +      {
> +        OUT_ATOMIC_OP(AND)
> +        OUT_ATOMIC_OP(OR)
> +        OUT_ATOMIC_OP(XOR)
> +        OUT_ATOMIC_OP(XCHG)
> +        OUT_ATOMIC_OP(INC)
> +        OUT_ATOMIC_OP(DEC)
> +        OUT_ATOMIC_OP(ADD)
> +        OUT_ATOMIC_OP(SUB)
> +        OUT_ATOMIC_OP(IMAX)
> +        OUT_ATOMIC_OP(IMIN)
> +        OUT_ATOMIC_OP(UMAX)
> +        OUT_ATOMIC_OP(UMIN)
> +        OUT_ATOMIC_OP(CMPXCHG)
> +        default:
> +          out << "." << "INVALID";
> +          assert(0);
> +      };
>        out << " %" << this->getDst(fn, 0);
>        out << " {" << "%" << this->getSrc(fn, 0) << "}";
>        for (uint32_t i = 1; i < srcNum; ++i)
> --
> 1.9.1
> 
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