[Beignet] [PATCH 4/5] GBE: don't always allocate ir::ocl::one/zero
Zhigang Gong
zhigang.gong at intel.com
Sun Sep 13 23:19:35 PDT 2015
Use liveness information, we can only allocate them
on demand. And they could be treated as non-curbe-payload
register.
Signed-off-by: Zhigang Gong <zhigang.gong at intel.com>
---
backend/src/backend/gen_context.cpp | 10 ++++------
backend/src/backend/gen_reg_allocation.cpp | 12 +++++++++---
backend/src/backend/gen_reg_allocation.hpp | 2 ++
backend/src/backend/program.h | 2 --
backend/src/ir/profile.cpp | 4 ++--
5 files changed, 17 insertions(+), 13 deletions(-)
diff --git a/backend/src/backend/gen_context.cpp b/backend/src/backend/gen_context.cpp
index 5980db2..3dbd957 100644
--- a/backend/src/backend/gen_context.cpp
+++ b/backend/src/backend/gen_context.cpp
@@ -160,8 +160,6 @@ namespace gbe
// when group size not aligned to simdWidth, flag register need clear to
// make prediction(any8/16h) work correctly
const GenRegister blockip = getBlockIP(*this);
- const GenRegister zero = ra->genReg(GenRegister::uw1grf(ir::ocl::zero));
- const GenRegister one = ra->genReg(GenRegister::uw1grf(ir::ocl::one));
p->push();
p->curr.noMask = 1;
p->curr.predicate = GEN_PREDICATE_NONE;
@@ -169,10 +167,10 @@ namespace gbe
p->curr.noMask = 0;
setBlockIP(*this, blockip, 0);
p->curr.execWidth = 1;
- // FIXME, need to get the final use set of zero/one, if there is no user,
- // no need to generate the following two instructions.
- p->MOV(zero, GenRegister::immuw(0));
- p->MOV(one, GenRegister::immw(-1));
+ if (ra->isAllocated(ir::ocl::zero))
+ p->MOV(ra->genReg(GenRegister::uw1grf(ir::ocl::zero)), GenRegister::immuw(0));
+ if (ra->isAllocated(ir::ocl::one))
+ p->MOV(ra->genReg(GenRegister::uw1grf(ir::ocl::one)), GenRegister::immw(-1));
p->pop();
}
diff --git a/backend/src/backend/gen_reg_allocation.cpp b/backend/src/backend/gen_reg_allocation.cpp
index 4430ca5..06f6cc7 100644
--- a/backend/src/backend/gen_reg_allocation.cpp
+++ b/backend/src/backend/gen_reg_allocation.cpp
@@ -102,6 +102,9 @@ namespace gbe
bool allocate(Selection &selection);
/*! Return the Gen register from the selection register */
GenRegister genReg(const GenRegister ®);
+ INLINE bool isAllocated(const ir::Register ®) {
+ return RA.contains(reg);
+ }
/*! Output the register allocation */
void outputAllocation(void);
INLINE void getRegAttrib(ir::Register reg, uint32_t ®Size, ir::RegisterFamily *regFamily = NULL) const {
@@ -1033,13 +1036,12 @@ namespace gbe
if (curbeType != GBE_GEN_REG) {
intervals[regID].minID = 0;
- // zero and one have implicitly usage in the initial block.
- if (curbeType == GBE_CURBE_ONE || curbeType == GBE_CURBE_ZERO)
- intervals[regID].maxID = 10;
// FIXME stack buffer is not used, we may need to remove it in the furture.
if (curbeType == GBE_CURBE_EXTRA_ARGUMENT && subType == GBE_STACK_BUFFER)
intervals[regID].maxID = 1;
}
+ if (regID == ir::ocl::zero.value() || regID == ir::ocl::one.value())
+ intervals[regID].minID = 0;
}
// Compute the intervals
@@ -1262,6 +1264,10 @@ namespace gbe
return this->opaque->genReg(reg);
}
+ bool GenRegAllocator::isAllocated(const ir::Register ®) {
+ return this->opaque->isAllocated(reg);
+ }
+
void GenRegAllocator::outputAllocation(void) {
this->opaque->outputAllocation();
}
diff --git a/backend/src/backend/gen_reg_allocation.hpp b/backend/src/backend/gen_reg_allocation.hpp
index 89dba64..8d5e797 100644
--- a/backend/src/backend/gen_reg_allocation.hpp
+++ b/backend/src/backend/gen_reg_allocation.hpp
@@ -54,6 +54,8 @@ namespace gbe
bool allocate(Selection &selection);
/*! Virtual to physical translation */
GenRegister genReg(const GenRegister ®);
+ /*! Check whether a register is allocated. */
+ bool isAllocated(const ir::Register ®);
/*! Output the register allocation */
void outputAllocation(void);
/*! Get register actual size in byte. */
diff --git a/backend/src/backend/program.h b/backend/src/backend/program.h
index 0758820..d364605 100644
--- a/backend/src/backend/program.h
+++ b/backend/src/backend/program.h
@@ -98,8 +98,6 @@ enum gbe_curbe_type {
GBE_CURBE_BLOCK_IP,
GBE_CURBE_DW_BLOCK_IP,
GBE_CURBE_THREAD_NUM,
- GBE_CURBE_ZERO,
- GBE_CURBE_ONE,
GBE_GEN_REG,
};
diff --git a/backend/src/ir/profile.cpp b/backend/src/ir/profile.cpp
index 484e82d..4486863 100644
--- a/backend/src/ir/profile.cpp
+++ b/backend/src/ir/profile.cpp
@@ -80,8 +80,8 @@ namespace ir {
DECL_NEW_REG(FAMILY_DWORD, barrierid, 1);
DECL_NEW_REG(FAMILY_DWORD, threadn, 1, GBE_CURBE_THREAD_NUM);
DECL_NEW_REG(FAMILY_DWORD, workdim, 1, GBE_CURBE_WORK_DIM);
- DECL_NEW_REG(FAMILY_DWORD, zero, 1, GBE_CURBE_ZERO);
- DECL_NEW_REG(FAMILY_DWORD, one, 1, GBE_CURBE_ONE);
+ DECL_NEW_REG(FAMILY_DWORD, zero, 1);
+ DECL_NEW_REG(FAMILY_DWORD, one, 1);
DECL_NEW_REG(FAMILY_WORD, retVal, 1);
DECL_NEW_REG(FAMILY_DWORD, printfbptr, 1, GBE_CURBE_PRINTF_BUF_POINTER);
DECL_NEW_REG(FAMILY_DWORD, printfiptr, 1, GBE_CURBE_PRINTF_INDEX_POINTER);
--
1.9.1
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